User`s manual

DIGITAL-LOGIC AG MSLB-P5 Manual V0.3
PRELIMINARY 161
16.5.3 Test Points and Beep Codes
At the beginning of each POST routine, the BIOS outputs the test point error code to I/O address 80h.
Use this code during trouble shooting to establish at what point the system failed and what routine was
being performed.
Some motherboards are equipped with a seven-segment LED display that displays the current value
of port 80h. For production boards which do not contain the LED display, you can purchase a card that
performs the same function.
If the BIOS detects a terminal error condition, it halts POST after issuing a terminal error beep code
(See above) and attempting to display the error code on upper left corner of the screen and on the
port 80h LED display. It attempts repeatedly to write the error to the screen. This may cause "hash" on
some CGA displays.
If the system hangs before the BIOS can process the error, the value displayed at the port 80h is the
last test performed. In this case, the screen does not display the error code.
The following is a list of the checkpoint codes written at the start of each test and the beep
codes issued for terminal errors. Unless otherwise noted, these codes are valid for Phoenix-
BIOS 4.0 Release 6.x.
Code Beeps POST Routine Description
02h Verify Real Mode
03h Disable Non-Maskable Interrupt (NMI)
04h Get CPU type
06h Initialize system hardware
07h Disable shadow and execute code from the ROM.
08h Initialize chipset with initial POST values
09h Set IN POST flag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize caches to initial POST values
0Eh Initialize I/O component
0Fh Initialize the local bus IDE
10h Initialize Power Management
11h Load alternate registers with initial POST values
12h Restore CPU control word during warm boot
13h Initialize PCI Bus Mastering devices
14h Initialize keyboard controller
16h 1-2-2-3 BIOS ROM checksum
17h Initialize cache before memory Autosize
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt Controller
20h 1-3-1-1 Test DRAM refresh
22h 1-3-1-3 Test 8742 Keyboard Controller
24h Set ES segment register to 4 GB
28h Autosize DRAM
29h Initialize POST Memory Manager
2Ah Clear 512 kB base RAM
2Ch 1-3-4-1 RAM failure on address line xxxx*
2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of
memory bus
2Fh Enable cache before system BIOS shadow
32h Test CPU bus-clock frequency
33h Initialize Phoenix Dispatch Manager
36h Warm start shut down
38h Shadow system BIOS ROM
3Ah Autosize cache