User`s manual
DIGITAL-LOGIC AG MSLB-P5 Manual V0.3
PRELIMINARY 133
Feature Options Description
External Cache Enabled
Disabled.
Generally enables or disables all mem-
ory caching.
Cache Interleave Enabled
Disabled
Interleaving multiple banks of static
RAM improves CPU access.
Cache Write Back
Enabled
Disabled
Enabled caches both reads and writes to
memory. Disabled caches reads only.
Cache Read Cycles Chipset
Dependent
Sets the number of clock pulses for
reading from the cache. Shorter number
of pulses improves performance.
Cache Write Cycles Chipset
Dependent
Sets the number of clock pulses for
writing to the cache. Shorter number of
pulses improves performance.
Cache System BIOS
Enabled
Disabled
Caches the system BIOS and improves
performance.
Cache Video BIOS Enabled
Disabled
Caches the video BIOS and improves
performance.
Cache segments,
e.g., E800-EFFF
Enabled
Disabled
Controls caching of individual segments
of memory usually reserved for shad-
owing system or option ROMs
Non-cacheable regions:
Specifies areas of regular and extended
memory as non-cacheable regions.
Region 0, start 0
Multiples of 64
Multiples of 64 define start of non-
cacheable region 0 in kilobytes.
Region 0, size Disabled
Multiples of 64
Disabling makes this region available
for cache. Multiples of 64 define size of
non-cacheable region 0 in kilobytes.
Region 1, start
0
Multiples of 64
Multiples of 64 define start of non-
cacheable region 1 in kilobytes.
Region 1, size Disabled
Multiples of 64
Disabling makes this region available
for cache. Multiples of 64 define size of
non-cacheable region 1 in kilobytes.
WARNING: Incorrect settings can cause your system to malfunction.