CoreModule™ 420 PC/104 Single Board Computer Reference Manual P/N 5001808A Revision A
Notice Page NOTICE No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of Ampro Computers, Incorporated.
Contents Chapter 1 About This Manual......................................................................................................... 1 Purpose of this Manual ...................................................................................................................... 1 Reference Material ............................................................................................................................. 1 Related Ampro Products ......................................................
Contents Miscellaneous ...................................................................................................................................41 Real Time Clock (RTC) ................................................................................................................41 User GPIO Interface .....................................................................................................................41 Oops! Jumper (BIOS Recovery).................................................
Contents List of Tables Table 2-1. Major Integrated Circuit (Chips) Descriptions and Function .......................................... 10 Table 2-2. Connector Descriptions.................................................................................................. 11 Table 2-3. Jumper Settings ............................................................................................................. 12 Table 2-4. Ethernet Port (J2) LED Indicators....................................................
Contents vi Reference Manual CoreModule 420
Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the CoreModule™ 420 PC/104 single board computer (SBC) module. This manual contains information that permits designers to create an embedded system based on specific design requirements.
Chapter 1 About this Manual NOTE If you are unable to locate the datasheets using the links provided, go to the manufacturer's web site where you can perform a search using the chip datasheet number or name listed, including the extension, (htm for web page, pdf for files name, etc. Related Ampro Products The following items are directly related to successfully using the Ampro product you have just purchased or plan to purchase.
Chapter 1 About this Manual Other Ampro Products • ETX Family – These high-performance, compact, rugged Computer-on-Module (COM) solutions use various x86 processors from Celeron to Pentium® M CPUs in an ETX Revision 2.7 form factor to plug into your custom baseboard. Each ETX module provides standard peripherals, including dual Ultra/DMA 33/66/100 IDE, floppy drive interface, PCI bus, ISA bus, serial, parallel, PS/2 keyboard and mouse interfaces, 10/100BaseT Ethernet, USB ports, Video, and AC’97 audio.
Chapter 1 About this Manual • ReadySystem™ Family – The ReadySystem family is a series of high performance, low cost turnkey systems that come with a ReadyBoard product installed into a particular size ReadyBox enclosure with a specific size SODIMM, and a 2 ½" hard disk drive pre-loaded with one of Ampro's supported operating systems (Linux®, etc.).
Chapter 2 Product Overview This introduction presents general information about the PC/104 architecture and the CoreModule 420 single board computer (SBC). After reading this chapter you should understand: • PC/104 Concept • CoreModule 420 architecture • CoreModule 420 features • Major components • Connectors • Specifications PC/104 Architecture The PC/104 architecture affords a great deal of flexibility in system design.
Chapter 2 Product Overview Product Description The CoreModule 420 SBC is an exceptionally high integration, high-performance, 486-based PC compatible system in the PC/104 form factor. This rugged and high quality single board system contains all the component subsystems of a PC/AT motherboard plus the equivalent of several PC/AT expansion boards. In addition, the CoreModule 420 SBC includes a comprehensive set of system extensions and enhancements that are specifically designed for embedded systems.
Chapter 2 Product Overview • Compact Flash Socket ♦ Provides compact flash socket (Type I or II) ♦ Supports IDE compact flash cards ♦ Attached to Secondary IDE bus • Floppy Disk Controller ♦ Provides shared floppy/parallel port connector ♦ Supports two floppy drives ♦ Supports all standard PC/AT formats: 360 kB, 1.2 MB, 720 kB, 1.44 MB, 2.
Chapter 2 Product Overview • Video (LCD/CRT) Display Enhanced 2D graphics controller ♦ Supports BitBLT implementation for all 256 raster operations for Windows® support ♦ Supports all BLT transparency modes • Bitmap transparency • Pattern transparency • Source transparency • Destination transparency ♦ Supports 8, 16, 24, and 32-bit pixel depths ♦ Supports hardware clipping ♦ Supports fast line draw engine with anti-aliasing ♦ Supports fast triangle fill engine ♦ Supports 4-bit alpha bl
Chapter 2 Product Overview Block Diagram Figure 2-2 shows the functional components of the module. Memory (SDRAM) Video (CRT/TFT) Internal PCI Bus CPU Core STPC Atlas (Computer in a Chip) Ethernet Controller I2C Interface USB Port Speaker Serial Ports (Serial 1 & 2) HostPeripheral Interface GPIOs (8) IDE Devices (HDD, Compact Flash, CD-ROM, etc.
Chapter 2 Product Overview Major Integrated Circuits (ICs) Table 2-1 lists the major integrated circuits (ICs or chips), including a brief description of each, on the CoreModule 420 and Figure 2-3 shows the location of the major chips. Table 2-1. Major Integrated Circuit (Chips) Descriptions and Function Chip Type CPU (U14) Mfg. STMicroelectronics Model STPC ATLAS Description Embedded CPU – The combination of features in the CPU provide more than just a processor.
Chapter 2 Product Overview Connectors, Jumpers, and LEDs Connector Definitions Table 2-2 describes the connectors shown in Figures 2-4 to 2-6. Refer to Appendix B for part numbers. Table 2-2. Connector Descriptions Jack/Plug # Access Description P1A/1B & P1C/1D – Top/ PC/104 Bus Bottom 104-pin, 0.1", connectors used for PC/104 (ISA) bus J2 – Ethernet Top 8-pin, 0.1", connector used for the Ethernet interface J3 – Serial 1 (COM1) Top 10-pin, 0.
Chapter 2 Product Overview Jumper Definitions Table 2-3 describes the jumpers shown in Figure 2-5. Table 2-3.
Chapter 2 Product Overview JP6 JP7 JP9 JP8 JP1 JP4 JP5 2 JP1 J5 1 JP6 J14 9 10 J3 JP5 JP4 U35 U3 JP9 U12 U36 JP7 L5 J4 1 J8 JP8 U7 2 U9 U8 U10 U41 U40 Bytewide Socket (U5) Pin-1 U6 U11 U5 D1 D2 U14 J2 U15 Link/Activity LED (D1) Speed LED (D2) U13 J10 U16 J7 JP2 JP2 P1 CM420RFM_01c J11 2 1 3 J13 D8 J9 4 10 Figure 2-5.
Chapter 2 Product Overview Specifications Physical Specifications Table 2-5 gives the physical dimensions of the module and Figure 2-7 gives the mounting dimensions. Table 2-5. Weight and Footprint Dimensions Item Dimension Weight Height (upper surface) 0.0925 kg. (0.204 lbs.) 10.99 mm (0.43") See also Note on page 15. Width 90.2 mm (3.6") Length 95.9 mm (3.8") NOTE Height is measured from the upper board surface to the highest permanent component (PC/104 connector) on the upper board surface.
Chapter 2 Product Overview NOTE The CoreModule 420 is in violation of the PC/104 height limitations in two places on the bottom of the board. The voltage regulator (U19) exceeds the allowed height limitation by 0.085 inches and the compact flash socket (J12) exceeds the height limitation by 0.2 inches. See Figure 2-6. Power Specifications Table 2-6 provides the power requirements. Table 2-6.
Chapter 2 16 Product Overview Reference Manual CoreModule 420
Chapter 3 Hardware Overview This chapter discusses the chips and connectors of the module features in the following order: • CPU (U14) • Memory ♦ SDRAM (U7, U8, U9, U10) ♦ Flash Memory (U6) ♦ Bytewide socket (U5) • PC/104 (P1A, B, C, D) • IDE (J6) • Compact flash socket (J12) • Serial (J3, J9, J13, J14) • Floppy/Parallel (J4) • Utility (J5) ♦ Keyboard ♦ Mouse ♦ Battery ♦ Reset Switch ♦ Speaker • Ethernet (J2) • USB (J10) • Video (J11) • Miscellaneous ♦ Time of Day/RTC ♦ User GPIO (J
Chapter 3 Hardware CPU (U14) The CoreModule 420 uses an embedded microprocessor operating at 133 MHz, that combines a powerful x86 core and a selection of peripheral interfaces into one chip. The STPC Atlas integrates a standard 5th generation x86 core. It supports logic including PC/104, EIDE controllers and combines these with standard I/O interfaces to provide a PC compatible subsystem in a single chip.
Chapter 3 Hardware Table 3-1.
Chapter 3 Hardware Interrupt Channel Assignments The channel interrupt assignments are shown in Table 3-2. Table 3-2. Interrupt Channel Assignments Device vs IRQ No. 0 Timer X Keyboard 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Disable X Secondary Cascade X COM1 X Z COM2 X Z COM3 O O O O O O O D O O Z COM4 O O O O O O D O O O Z O O O O Z Floppy X O Parallel O O O D RTC X Prim. IDE D Z Sec.
Chapter 3 Hardware Address (hex) Subsystem 0040-0043 Programmable Interrupt Timer (Clock/Timer) 0060-0064 0070-0071 Keyboard Controller 0080-008F DMA Page 0094 RTC/ NMI enable Motherboard VGA enable 00A0-00A1 Slave Interrupt Controller (#2) 00C0-00DF Secondary DMA Controller (#2) 0102 VGA setup register 01F0-01F7 Primary IDE (configurable) 0170-0177 Secondary IDE (configurable) 0201 02E8-02EF Watchdog trigger (configurable, disabled by default) COM4 (configurable) 02F8-02FF COM2 (co
Chapter 3 Hardware PC/104 Bus Interface (P1A,B,C,D) The PC/104 Bus uses a 104-pin 0.1" connector interface. This interface connector will carry all of the appropriate PC/104 signals operating at clock speeds to 8.25 MHz. This interface connector is located on both the top and bottom of the module. Table 3-5.
Chapter 3 Hardware Pin # Signal Description (P1 Row A) 27 (A27) SA4 System Address 4 – Refer to SA19, pin A12, for more information. 28 (A28) SA3 System Address 3 – Refer to SA19, pin A12, for more information. 29 (A29) SA2 System Address 2 – Refer to SA19, pin A12, for more information. 30 (A30) SA1 System Address 1 – Refer to SA19, pin A12, for more information. 31 (A31) SA0 System Address 0 – Refer to SA19, pin A12, for more information.
Chapter 3 Hardware Pin # Signal Description (P1 Row B) 49 (B17) DACK1* DMA Acknowledge 1 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. 50 (B18) DRQ1 DMA Request 1 – Used by I/O resources to request DMA service. Must be held high until associated DACK1 line is active.
Chapter 3 Hardware Pin # Signal Description (P1 Row C) 6 (C5) LA20 Latchable Address 20 – Refer to LA23, pin C2, for more information. 7 (C6) LA19 Latchable Address 19 – Refer to LA23, pin C2, for more information. 8 (C7) LA18 Latchable Address 18 – Refer to LA23, pin C2, for more information. 9 (C8) LA17 Latchable Address 17 – Refer to LA23, pin C2, for more information. 10 (C9) MemR* Memory Read – This signal instructs a selected memory device to drive data onto the data bus.
Chapter 3 Hardware Pin # Signal Description (P1 Row D) 31 (D10) DACK5* DMA Acknowledge 5 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. 32 (D11) DRQ5 DMA Request 5 – Used by I/O resources to request DMA service. Must be held high until associated DACK5 line is active.
Chapter 3 Hardware IDE Interface (J6) The IDE device signals are provided through the standard 44-pin, 2 mm connector (J6). The IDE interface supports the following features: • Master mode PCI supporting Enhanced IDE devices • Supports two EIDE devices • Full scatter-gather capability • Supports ATAPI compliant devices including DVD • Supports IDE native and ATA compatibility modes Table 3-9 gives the signals for the 44-pins of the IDE 2 mm header. Table 3-9.
Chapter 3 Hardware Pin # Signal Description 25 PIOR* Drive I/O Read – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. 26 GND Ground 27 IOChRdy I/O Channel Ready – When negated, extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted.
Chapter 3 Hardware Compact Flash Socket Interface (J12) The CoreModule 420 provides a compact flash socket, which allows for the insertion of a compact flash card (Type I or II). The compact flash card acts as a standard IDE Drive and is the only device connected to the Secondary IDE bus. If a compact flash card is installed, it must be set in BIOS Setup as [CF on Sec Master] and is hardwired for master mode.
Chapter 3 Hardware Pin # Signal Description 27 D11 Disk Data 11 – Refer to pin 2, D3, for more information. 28 D12 Disk Data 12 – Refer to pin 2, D3, for more information. 29 D13 Disk Data 13 – Refer to pin 2, D3, for more information. 30 D14 Disk Data 14 – Refer to pin 2, D3, for more information. 31 D15 Disk Data 15 – Refer to pin 2, D3, for more information.
Chapter 3 Hardware Floppy/Parallel Interface (J4) Floppy Disk Drive Port The Super I/O chip provides the Floppy Disk Controller and the Parallel Port interface (J4). The Floppy Drive interface shares the same connector as the Parallel Port and the signals are multiplexed out of the connector. However, you can only use one of these devices at a time and it must be configured in BIOS Setup Utility. The default device in the BIOS Setup Utility is the Floppy Drive.
Chapter 3 Hardware Pin # Signal Description 8 SLIN Select In – This output signal is used to select the printer. I/O pin in ECP/EPP mode. STEP Step – Low step pulse for each track-to-track movement of the head. PD3 Parallel Port Data 3 – Refer to pin-3, PDO for more information. RDATA Read Data – Raw serial bit stream from the drive for read operations. 10 GND Ground 11 PD4 Parallel Port Data 4 – Refer to pin-3, PDO for more information.
Chapter 3 Hardware Serial Interface (J3, J9, J13, J14) The Atlas CPU and Super I/O chips each contain the circuitry for two of the four serial ports. The Atlas CPU provides serial port 1 (J3) and serial port 2 (J9) through the two independent 10-pin connectors. The Super I/O chip provides serial ports 3 (J13) and 4 (J14).
Chapter 3 Hardware Table 3-12. Serial Ports 1 & 2 Interface Pin/Signal Descriptions (J3, J9) Pin # Signal DB9 # Description 1 DCD* 1 Data Carrier Detect – Indicates external serial device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR as part of the DTR/DSR handshake. 2 DSR* 6 Data Set Ready – Indicates external serial device is powered, initialized, and ready.
Chapter 3 Hardware Pin # Signal DB9 # Description 4 RTS* 7 Request To Send – Indicates serial port is ready to transmit data. Used as hardware handshake with CTS for low level flow control. 5 TXD 3 Transmit Data – Serial port transmit data output is typically held to a logic 1 when no data is being sent. Typically, a logic 0 (On) must be present on RTS, CTS, DSR, and DTR before data can be transmitted on this line.
Chapter 3 Hardware Utility Interface (J5) The Utility interface provides various utility and I/O signals on the module and consist of a 10-pin, 0.1" header. The Super I/O chip drives most of the signals on the Utility interface. Table 3-15 provides the definition of the interface signals on the utility interface.
Chapter 3 Hardware Ethernet Interface (J2) The Ethernet solution is provided by the Intel 82559ER PCI controller chip and consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82559ER is a glueless 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82559ER to perform high-speed data transfers over the internal PCI bus.
Chapter 3 Hardware Video (LCD/CRT) Interface (J11) The STPC Atlas chip provides the 2D graphics controller for the video signals to a flat panel display and traditional glass CRT monitor.
Chapter 3 Hardware Table 3-17. Video Interface Pin/Signal Descriptions (J11) Pin # Signal Description TFTDCLK TFT Shift Clock – This clock signal provides the timing for transferring digital 1 pixel data. TFTDE TFT Data Enable – This signal indicates valid data on any of the FP [23:0] lines. 2 3 TFTLP TFT Line Pulse – This signal is the digital monitor equivalent of HSYNC. 4 TFTFrame TFT Frame Marker – This signal is the TFT monitor equivalent of VSYNC.
Chapter 3 Hardware Pin # Signal VSYNC 38 39 AGNDR Description Vertical Sync – This signal is used for the digital vertical sync output to the CRT. Also used (with HSYNC) to signal power management state information to the CRT per the VESA™ DPMS™ standard. Analog Ground for Red 40 RED Red – This pin provides the Red analog output to the CRT. 41 AGNDG Analog Ground for Green 42 GREEN Green – This pin provides the Green analog output to the CRT.
Chapter 3 Hardware Miscellaneous Real Time Clock (RTC) The CoreModule 420 contains a Real Time (time of day) Clock (RTC), which can be backed up with an external Lithium Battery. The CoreModule 420 will function without a battery in those environments, which prohibit inclusion of batteries. The CoreModule 420 will also continue to operate after the battery life has been exceeded.
Chapter 3 Hardware Oops! Jumper (BIOS Recovery) The Oops! jumper is provided in the event you’ve selected BIOS settings that prevent you from booting the system. By using the Oops! jumper you can stop the current BIOS settings in the CMOS from being loaded, allowing you to proceed, using the default settings. Connect the DTR pin to the RI pin on Serial port 1 (COM 1) prior to boot up to prevent the present BIOS settings from loading.
Chapter 3 Hardware Watchdog Timer The watchdog timer (WDT) restarts the system if an error or mishap occurs, allowing the system to recover from the mishap, even though the error condition may still exist. Possible problems include failure to boot properly, loss of control by the application software, failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions.
Chapter 3 Hardware Power Interface (J7) The CoreModule 420 requires one +5 volt DC power source and uses a 10-pin header with 0.1" spacing. If the +5VDC power drops below ~4.65V, a low voltage reset is triggered, resetting the system. The power input connector (J7) supplies the following voltages and ground directly to the module: • 5.0VDC +/- 5% @ 1.35 Amps Table 3-19 gives the signals for Power supply pin outs. Table 3-19.
Chapter 4 BIOS Setup Introduction This chapter describes the BIOS Setup menus and the various screens used for configuring the CoreModule 420. Some features in the Operating System (OS) or application software may require configuration in the BIOS Setup screens. This section assumes the user is familiar with general BIOS setup and does not attempt to describe the BIOS functions. Refer to the appropriate PC reference manuals for information about the software interface of the onboard ROM BIOS.
Chapter 4 BIOS Setup Accessing BIOS Setup (Serial Console) Entering the BIOS Setup, in serial console (console redirection) mode, is very similar to the steps you use to enter BIOS Setup with a VGA display input, except the actual keys you use. 1. Set the serial terminal, or the PC with communications software to the following settings: ♦ 115k baud ♦ 8 bits ♦ One stop bit ♦ No parity ♦ No hardware handshake 2.
Chapter 4 BIOS Setup Main BIOS Setup Menu Ampro Setup Utility for CoreModule 420, SWxxxxxx Help for BIOS and Hardware Settings > BIOS and Hardware Settings < Reload Initial Settings Load Factory Default Settings Exit, Saving Changes Exit, Discarding Changes Use Arrow keys to change menu item, use Enter to select menu item (C) Copyright 2004, Ampro Computers, Inc. - http://www.ampro.com Figure 4-1.
Chapter 4 BIOS Setup BIOS Configuration Screen Ampro Setup Utility for CoreModule 420, SWxxxxxx [Date & Time] > Date 28 Jun 2006< Time 10:24:34 [Drive Assignment] Drive A 1.44 MB, 3.5” Drive B (none) Drive C HDD on Pri Master (none) Drive D (none) Drive E [Boot Order] Boot 1st Drive A: Boot 2nd Drive C: Boot 3rd CDROM (none) Boot 4th (none) Boot 5th Boot 6th (none) [Drive and Boot Options] Help for Date The Date & Time fields are updated in real-time.
Chapter 4 BIOS Setup • Boot Order ♦ Boot 1st – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], [Reboot], or [Flash] ♦ Boot 2nd – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], [Reboot], or [Flash] ♦ Boot 3rd – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], [Reboot], or [Flash] ♦ Boot 4th – [none], [Drive A], [Drive B], [Drive C], [Drive D], [CDROM], [Alarm], [Reboot], or [Flash] ♦ Boot 5th – [none], [Drive A], [Drive B], [Drive C
Chapter 4 BIOS Setup User Interface Options • Keyboard and Mouse ♦ Numlock – [Disabled] or [Enabled] ♦ Typematic – [Disabled] or [Enabled] These fields are used to set parameters for the keyboard. • Delay – [250ms], [500ms], [750ms], or [1000ms] This field determines how many milliseconds the keyboard controller waits before stating to repeat a key, if the key is held down on the keyboard.
Chapter 4 BIOS Setup Power Management and Advanced User Options • Power Management ♦ APM – [Disabled] or [Enabled] • Advanced features ♦ Post Memory Manager – [Disabled] or [Enabled] ♦ Watchdog Timeout (sec) – [select whole number between 1 and 255 seconds] or [Disabled] ∗ If this feature is enabled by selecting a timer interval, it will direct the watchdog timer to reset the system if the OS fails to boot the system within the timer interval specified.
Chapter 4 BIOS Setup Video and On Board Controller Options • On-Board Video ♦ Framebuffer Size – [Disabled], [1MB], [2MB], [3MB], or [4MB] This field specifies the amount of system memory used for the on-board Video Framebuffer. The amount of memory used for the Framebuffer of the on-board Video controller is subtracted from the available system memory. NOTE ♦ If the Framebuffer Size field is set to [Disabled], then no video will be displayed on screen.
Chapter 4 BIOS Setup ♦ Assign IRQ 4 – [Disabled] or [Enabled] (Typically COM1) ∗ If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter. ∗ If another device in the system is using this IRQ, then this field should be set to [Disabled]. ♦ Assign IRQ 5 – [Disabled] or [Enabled] ∗ If this field is set to [Enabled], then the BIOS can assign this IRQ to a Plug and Play adapter.
Chapter 4 BIOS Setup ♦ Assign DMA 2 – [Disabled] or [Enabled] ∗ If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter. ∗ If another device in the system is using this DMA channel, then this field should be set to [Disabled]. ♦ Assign DMA 3 – [Disabled] or [Enabled] ∗ If this field is set to [Enabled], then the BIOS can assign this DMA channel to a Plug and Play adapter.
Chapter 4 BIOS Setup Splash Screen Customization The CoreModule 420 BIOS supports a graphical splash screen, which can be customized by the user and displayed on screen when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any custom image the user wants to display during the boot process. The custom image can be displayed as the first image displayed on screen during the boot process and remain there, depending on the options selected in BIOS Setup, while the OS boots.
Chapter 4 BIOS Setup Use the following steps to convert and load your custom image onto the CoreModule 420. 1. Copy the files from the CD-ROM\Software\Misc\Splash directory on the CD-ROM to a new directory (conversion directory) on your PC. This new conversion directory is where you intend to do the conversion and save the file. 2. Ensure you remove the read-only attributes from all the files as part of the file copying process. 3. Copy the CoreModule 420 BIOS binary file (cm420.
Chapter 4 BIOS Setup On-Board Flash Access and Use This section describes how to use the on-board flash memory and load an application in the available lower 768 kB region of the 1 MB of flash memory. The application can boot directly from the on-board flash memory. The flash memory can be accessed at 128 MB intervals above the base address (with the exception of 256 MB). For example, if the flash address is set to 8 MB, then the flash memory can be accessed at 136 MB, 392 MB, 520 MB etc.
Chapter 4 BIOS Setup Example Assumptions The following assumptions have been made concerning the application and certain functionality has not implemented. • The application is located at the fixed address of 1 MB. • The bootloader has to load the application at the fixed address of 1 MB. • The startup code is incomplete. For example, early initialization functions and constructors normally called before main, are not called at all. • In general, the standard libraries can NOT be used.
Appendix A Technical Support Ampro Computers, Inc. provides a number of methods for contacting Technical Support listed below in Table A-1. Requests for support through the Virtual Technician are given the highest priority, and usually will be addressed within one working day. • Ampro Virtual Technician – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro web site at http://ampro.custhelp.com.
Appendix A 60 Technical Support Reference Manual CoreModule 420
Appendix B Connector Part Numbers Table B-1 provides the non-standard RoHS connectors, including the manufacturers and part numbers, used on the CoreModule 420. These part numbers can be used to determine the mating connectors, when making your own cables. Table B-1. Connector and Manufacture’s Part Numbers Connector Pin Number/Pin Spacing/ Orientation Manufacturer Manufacturer’s PN J2 – Ethernet 8-pin, 0.1", right angle AMP/Tyco 3-647079-8 J3 – Serial 1, 10-pin, 0.
Appendix B 62 Connector Part Numbers Reference Manual CoreModule 420
Index Ampro Products CoreModule™ 410 ............................................ 2 CoreModule™ 600 ............................................ 2 CoreModule™ 800 ............................................ 2 ETX Family....................................................... 3 LittleBoard™ Family......................................... 3 MightyBoard ™ Family..................................... 3 MiniModule™ Family ....................................... 3 ReadyBoard™ Family ...............................
Index compact flash socket........................................ 29 connector locations .......................................... 11 connector part numbers ................................... 63 CPU features................................................ 6, 18 current capability ............................................. 44 dimensions....................................................... 14 DiskOnChip (DOC) settings............................ 50 DMA map.............................................
Index no bootable device available ............................... 51 null modem serial cable................................. 42, 53 Oops! jumper DB9 connector................................................. 42 Serial port 1 ..................................................... 42 Parallel (LPT1) port features ............................................................ 31 settings............................................................. 53 supported protocols ...................................
Index Utility connector .............................................. 36 video setting, onboard...................................... 54 video (CRT) interface...................................... 38 video (CRT) interface (1) ............................ 8, 38 video (LCD) interface (1) ............................ 8, 38 video port interface (1) ................................ 8, 38 watchdog timer (WDT) ......................... 8, 43, 53 terminal emulation software serial console ........................
