Instruction manual

AMPDIO DRIVERS
Page 78
of Z1 channel 1, and the /OUT n–2 gate source for Z1 channel 0 comes from the output of Z2
channel 1.
For the PCI230 and PCI230+, the Z2 counter/timer’s GAT inputs are connected internally to PPI-X
C0, C1 and C2. For the PCI260+, all three counter/timer GAT inputs are connected internally to the
external trigger input (SK1 pin 17). For the original PCI260, PCI224 and PCI234, the GAT input is
not connected.
BIT ASSIGNMENTS
Bit layout of each gate connection register is shown below.
Additional Gate Sources for PCI230+ and PCI260+
The PCI230+ and PCI260+ cards support the following additional gate sources:
1. Latched GAT n — starts low and goes high on rising edge of timer/counter’s GAT input
2. Latched /GAT n — starts low and goes high on falling edge on timer/counter’s GAT input
3. /GAT n — inverted timer/counter’s GAT input
4. OUT n–2 — the non-inverted output of counter timer n–2
0 1 2 3 4 5 6 7
bit 2 bit 1 bit 0 Gate Source
0 0 0 VCC
0 0 1 GND
0 1 0 GAT n
0 1 1 /OUT n–2
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
bit 4 bit 3 Counter/Timer
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Reserved
bit 5 Counter/Timer Device
0 X1/Y1/Z1
1 X2/Y2/Z2
bit 7 bit 6
X X Reserved
bit 2 bit 1 bit 0 Gate Source
0 0 0 VCC
0 0 1 GND
0 1 0 GAT n
0 1 1 /OUT n–2
1 0 0 Latched GAT n
1 0 1 Latched /GAT n
1 1 0 /GAT n
1 1 1 OUT n-2