Instruction manual

AMPDIO DRIVERS
Page 77
BIT ASSIGNMENTS
Bit layout of each clock connection register is shown below.
5.4.3.2 Group Gate Connection Registers
These registers can be used to select the counter/timer gate input sources for each counter/timer
channel.
Register
Offset
Write and/or
Read
Register
Width
Register
Title
Mnemonic
03
16
Write 8 bits
Group X Counter/timer Gate
Selection Register
XGAT_SCE
04
16
Write 8 bits
Group Y Counter/timer Gate
Selection Register
YGAT_SCE
05
16
Write 8 bits
Group Z Counter/timer Gate
Selection Register
ZGAT_SCE
FUNCTION
Individually selects one of the four possible Counter/Timer gate input signal sources for each
counter/timer channel.
The Four Gate Sources
The four
1
possible gate sources are as follows:
1. VCC (internal +5V d.c.) — i.e. gate permanently enabled
2. GND (internal 0V d.c.) — i.e. gate permanently disabled
3. GAT n — the counter/timer’s GAT input from the SK1 connector
4. /OUT n–2 — the inverted output of counter timer n–2
N.B. The n–2 channel for channel 0 on a particular counter/timer chip is channel 1 of the preceding
counter/timer chip, and the n–2 channel for channel 1 on a particular counter/timer chip is channel
2 of the preceding counter/timer chip. The highest counter/timer chip is considered to precede the
lowest counter/timer chip for this purpose. For example, on the PC215E, which has two
counter/timer chips, Z1 and Z2, the /OUT n–2 gate source for Z2 channel 0 comes from the output
1
Some cards support up to four additional gate sources.
0 1 2 3 4 5 6 7
bit 2 bit 1 bit 0 Clock Source
0 0 0 CLK n
0 0 1 10 MHz
0 1 0 1 MHz
0 1 1 100 kHz
1 0 0 10 kHz
1 0 1 1 kHz
1 1 0 OUT n–1
1 1 1 Ext Clock
bit 4 bit 3 Counter/Timer
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Reserved
bit 5 Counter/Timer Device
0 X1/Y1/Z1
1 X2/Y2/Z2
bit 7 bit 6
X X Reserved