Instruction manual

AMPDIO DRIVERS
Page 76
5.4.3.1 Group Clock Connection Registers
These registers can be used to select the counter/timer clock sources.
Register
Offset
Write and/or
Read
Register
Width
Register
Title
Mnemonic
00
16
Write 8 bits
Group X Counter/timer
Clock Selection Register
XCLK_SCE
01
16
Write 8 bits
Group Y Counter/timer
Clock Selection Register
YCLK_SCE
02
16
Write 8 bits
Group Z Counter/timer
Clock Selection Register
ZCLK_SCE
FUNCTION
Individually selects one of the eight possible Counter/Timer clock sources for each counter/timer
channel.
The Eight Clock Sources
The eight possible clock sources are as follows:
1. The counter/timer’s CLK input from the SK1 connector
2. The internal 10 MHz clock
3. The internal 1 MHz clock
4. The internal 100 kHz clock
5. The internal 10 kHz clock
6. The internal 1 kHz clock
7. The output of the preceding counter/timer channel (OUT n–1)
8. The dedicated external clock input for the group (X1/X2, Y1/Y2 or Z1/Z2)
N.B. The preceding counter/timer channel for channel 0 on a particular counter/timer chip is
channel 2 of the preceding counter/timer chip. The highest counter/timer chip is considered to
precede the lowest counter/timer chip for this purpose. For example, on the PC215E, which has
two counter/timer chips, Z1 and Z2, the OUT n–1 clock source for Z2 channel 0 comes from the
output of Z1 channel 2, and the OUT n–1 clock source for Z1 channel 0 comes from the output of
Z2 channel 2.