Instruction manual

AMPDIO DRIVERS
Page 75
Read-Back Command
D7 D6 D5 D4 D3 D2 D1 D0
1 1 /COUNT /STATUS CNT2 CNT1 CNT0 0
D5: 0 = Latch count of selected Counter(s)
D4 0 = Latch status of selected Counter(s)
D3 1 = Select Counter 2
D4 1 = Select Counter 1
D5 1 = Select Counter 0
N.B. The Read-Back Command is not supported by the 82C53. Prior to AMPDIO v4.23, The driver
uses the Read-Back Command to latch counters, so reading counters is not reliable on those
cards which use the 82C53.
Latching the count of selected channels with the Read-Back Command has the same effect as the
Counter Latch Command on those channels.
If the status of a counter is latched, the next read from that counter’s register will read and unlatch
the status. Otherwise, if the count of a channel is latched, the next 1 or 2 reads from that counter’s
register (depending on the Read/Write configuration) will read 1 or 2 halves of the counter value
and unlatch the count.
The counter status format is shown below.
D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT NULL
COUNT
RW1 RW0 M2 M1 M0 BCD
D7 1 = OUT pin is 1
0 = OUT pin is 0
D6 1 = Null count
0 = Count available for reading
D5–D0 Counter programmed mode
Further information on programming the 82C54 Programmable Counter/Timer can be found in
chapters 5 and 2. For a full description of the six operating modes and all other features of the
82C54, see the manufacturer's data sheet for the 82C54 in the appendices on the SOFTMAN CD.
5.4.3 Clock and Gate Configuration Registers
Clock and counter timer connection registers have the following configuration. Offsets are from the
start of the CT Control block in the register map (18
16
on all supported cards):
Port Offset Description Access Bits
00
16
Clock Connections for group X timers W 8
01
16
Clock Connections for group Y timers W 8
02
16
Clock Connections for group Z timers W 8
03
16
Gate Connections for group X timers W 8
04
16
Gate Connections for group Y timers W 8
05
16
Gate Connections for group Z timers W 8