Instruction manual

AMPDIO DRIVERS
Page 74
Mode 4 Software Triggered Mode
Mode 5 Hardware Triggered Strobe (Re-triggerable)
BIT ASSIGNMENTS
The bit layout of the counter timer control register is shown below.
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
SC – Select Counter
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read-Back Command (See Below)
RW – Read/Write
RW1 RW0
0 0 Counter Latch Command (See Below)
0 1 Read/Write least significant byte only.
1 0 Read/Write most significant byte only.
1 1 Read/Write least significant byte first, then most significant byte.
M – Mode
M2 M1 M0
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
BCD – Binary Coded Decimal
0 Binary Counter 16-bits
1 Binary Coded Decimal (BCD) Counter (4 Decades)
The format of the Counter Latch Command and Read-Back Command are shown below.
Counter Latch Command
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 X X X X
SC1, SC0 specify counter to be latched:
SC1 SC0 COUNTER
0 0 0
0 1 1
1 0 2
1 1 Read-Back Command