Instruction manual

AMPDIO DRIVERS
Page 62
5 STRUCTURE AND ASSIGNMENTS OF THE REGISTERS
In order to gain the maximum out of the ADIO driver it is useful to have an appreciation of the
underlying register locations. The driver was originally developed for the series 200 DIO cards and
the register structure used on those cards forms the fundamental basis of the driver architecture.
5.1 Register Assignments on Series 200 DIO Cards
The series 200 registers occupy 32 consecutive address locations in the I/O space. A table
summarising the register assignments is shown in section 5.3. Please note that the actual register
address is the base address configured on the board plus the register offset given in the table.
5.2 Register Grouping
All the DIO boards in the 200 series, PC212E, PC214E, PC215E, PC218E, PC272E, PCI215 and
PCI272 series have the same register map, which is split up into five groups. Other supported
cards are fit into the same grouping scheme as far as possible.
5.2.1 Cluster X, Y and Z Groups
Each of the Cluster X, Y and Z groups is populated with either an 82C55 Programmable Peripheral
Interface (PPI) device to provide digital input/output, or two 82C54 Counter/Timer devices. Each of
the boards in the range deploys various combinations of these devices. The analogue I/O cards
still support this idea, but other resources can be found in the X,Y, Z groups.
5.2.2 Counter Connection Register Group
The Counter Connection Register (CT) group is supported by the PC212E, PC215E, PC218E and
PCI215 series 200 boards and the PCI230, PCI260, PCI224, PCI234 PCI analogue I/O cards.
These registers provide software-programmable clock and gate connections for the on-board
counter/timer groups. Other supported cards allow selection of the timer/counter clock source by
means of jumpers, and do not provide gate source selection.
5.2.3 Interrupts Group
Most of the supported cards have an interrupt enable (IE) register. This register provides
programmable interrupt source selection and interrupt status information. On cards which do not
have an interrupt enable/ interrupt status register, only one interrupt source should be used at a
time. Sometimes the interrupt source is selected by means of a jumper on these cards.
5.3 The Drivers View of The Register Layout
The driver divides the I/O space into 8 I/O blocks; the first 6 blocks can be 82C54 counter timers
(CT) or 82C55 programmable peripheral interfaces (PPI) or analogue I/O or empty, depending on
which card is installed. The next block is the counter timer clock and gate connection block and the
last is the interrupt enable block.
Most cards fit into this generalised I/O structure, but some cards do not support the counter timer
clock and gate connection block, or the interrupt enable block.