Instruction manual

AMPDIO DRIVERS
Page 49
across equal periods of time, i.e. the time between sampling the first channel and the next channel
is the same as the time between sampling the last channel and the first channel of the next cycle.
For some applications it is desirable to read all the desired channels in a short period, then have a
long gap before starting the next reading cycle. On the PCI230 and PCI260, this may be
accomplished by using the periodic pulse train generation functions introduced in version 4.32 of
the library. The more general of these functions, TCsetPeriodicPulseTrain (see section 6.4.8.7)
allows the number of pulses in each pulse train, the duration of each pulse train and the frequency
of pulse trains to be set. Normally, the number of pulses in each train would be set to the number
of channels being read.
If the set of channels is to be sampled at a fairly low frequency, the buffer length specified in the
call to the user interrupt set-up function can also be set to the number of channels, then the user
interrupt callback function will be called once for each set of readings. The user interrupt set-up
function should be set to use ‘continuous’ mode.
There is a restricted version of the periodic pulse train generator provided by the
TCsetRestrictedPulseTrain function (see section 6.4.8.14) which is similar but provides much less
control over the duration of the pulse train, typically a duration of 1 ms or 100 µs would be used for
the PCI230 or PCI260 and all the desired channels would be sampled over this period.
It is also possible to read a set of channels on a hardware trigger using the
TCsetOneShotPulseTrain function (see section 6.4.8.20), rather than read them periodically. This
trigger could be provided by the output of another timer/counter channel rather than an external
trigger signal. This is effectively how the TCsetPeriodicPulseTrain function is implemented. Another
possibility would be to use a timer/counter to implement a delay after an external hardware trigger
using timer/counter mode 5 (hardware triggered strobe).
On previous versions of the PCI230 and PCI260 cards there is a problem using the controlled
timing mechanisms. This is fixed in hardware on PCI230 cards bearing a sticker labelled
PR989386.4 on chip U19, and on PCI260 cards bearing a sticker labelled PR989385.4 on chip
U19. A software workaround can be used with caution on older cards in some circumstances.
The problem on older versions of the cards is due to the possibility of an ADC conversion being
triggered by a change to the configured value of the ADC conversion trigger source (e.g. by the
function AIOsetADCconvSource — see section 6.4.19.1). If the old conversion trigger source was
at a low logic level and the new conversion trigger source is at a high logic level and ADC
conversion is triggered. (N.B. the conversion trigger source CNV_NONE is always at a low-logic
level; the conversion trigger source CNV_SW is at a low logic level except at the time of the actual
software trigger.) This is a problem when setting the conversion trigger source to one of the timer
channels (CNV_CT0, CNV_CT1 or CNV_CT2) as a conversion trigger may or may not occur at
this time (depending on the state of the timer’s output). This does not affect the correspondence
between buffer positions and channels but does affect the position of the long gap within the
sequence of channel readings.
The bogus ADC trigger can also occur at the start of each user interrupt data buffer if single
buffering (as opposed to double buffering) is used. In single buffer mode, the driver resets the ADC
FIFO and this process involves temporarily setting the conversion trigger source to CNV_NONE. A
bogus trigger can occur when the conversion trigger source is reset to the configured value.
As a software workaround, there is a function TCflushUserInterrupt (see section 6.4.16.2) that may
be called to reset the ADC FIFO (amongst other things) to work around the problem. This function
should be used with caution as it uses a partial FIFO reset sequence (it does not set the
conversion trigger source to CNV_NONE) that can cause the correspondence between ADC
channels and buffer positions to be lost. To avoid this, the caller must use some means to ensure
that an ADC conversion cannot be triggered during this function call, and it must do that without
reconfiguring the conversion trigger source temporarily before the function call. This workaround is
particularly tricky for single buffer mode interrupts due to the possibility of the bogus trigger