Instruction manual

AMPDIO DRIVERS

Page 35

There are also lower level functions available. These functions were first implemented in version

2.0x of the library. They allow direct programming of the 82C55 ports without using the channel

concept and allow modes 1 and 2 to be selected. The extra functions are DIOsetModeEx,

DIOgetModeEx, DIOgetDataEx and DIOsetDataEx (see sections 6.4.11.7, 6.4.11.8, 6.4.11.9 and

6.4.11.10). With these functions, the supplied value is written directly to the associated 82C55

device. The function of the 82C55 is detailed in section 5.4.1.

The 82C55 chip is normally operated in mode 0. The DIOsetModeEx function (see section

6.4.11.7) can be used to write an arbitrary value to the 82C55’s control port. This can be a mode-

setting command or a single bit set/reset command (useful in modes 1 and 2).

Setting the mode using the DIOsetMode or DIOsetModeEx functions causes all configured output

bits to be set to the logic level 0 (0V).

3.2.2 Switch Matrix

The high numbers of digital I/O channels available on the 82C55 PPI devices lend themselves to a

switch matrix scanner implementation. The status of a matrix of switches can be obtained by

sending test patterns into the matrix, and then reading status patterns back from the matrix.

Section 6.4.12 describes functions that allow PPIX, both PPIX and PPIY, or PPIX, PPIY and PPIZ

to be used as such a device. Using only PPIX, up to 144 switches can be scanned; using both

PPIX and PPIY, up to 576 switches can be scanned; using PPIX, PPIY and PPIZ, up to 1296

switches can be scanned. Group ‘A’ ports of the 82C55 device(s) (Port A and Port C-upper) are set

for output to send test patterns to the matrix. Group ‘B’ ports (Port B and Port C-lower) are set for

input to read the switch status information. The user must ensure that the switch matrix is wired as

detailed below.

GND

1N4448

SPST SPST

10k 10k

SPST SPST

PPI X A0

PPI X A1

PPI X B0

PPI X B1

etc., up to PPI X A7,

then C4 to C7, then

onto PPI Y, and PPI Z.

etc., up to PPI X B7,

then C0 to C3, then

onto PPI Y, and PPI Z.

Figure 1 – Switch Matrix Configuration