Instruction manual
Table Of Contents
- INTRODUCTION
- GETTING STARTED
- MAKING THE CONNECTIONS
- USING THE PC215E
- STRUCTURE AND ASSIGNMENTS OF THE REGISTERS
- Register Assignments
- Register Groups
- The Register Details
- Programmable Peripheral Interface PPI-X Data Register Port A
- Programmable Peripheral Interface PPI-X Data Register Port B
- Programmable Peripheral Interface PPI-X Data Register Port C
- Programmable Peripheral Interface PPI-X Command Register
- Programmable Peripheral Interface PPI-Y Data Register Port A
- Programmable Peripheral Interface PPI-Y Data Register Port B
- Programmable Peripheral Interface PPI-Y Data Register Port C
- Programmable Peripheral Interface PPI-Y Command Register
- Z1 Counter 0 Data Register
- Z1 Counter 1 Data Register
- Z1 Counter 2 Data Register
- Counter/Timer Z1 Control Register
- Z1 Counter/Timer Status Register
- Z2 Counter 0 Data Register
- Z2 Counter 1 Data Register
- Z2 Counter 2 Data Register
- Counter/Timer Z2 Control Register
- Z2 Counter/Timer Status Register
- Group Z Clock Connection Register
- Group Z Gate Connection Register
- Interrupt Source Selection Register
- Interrupt Status Register
- PROGRAMMING THE PC215E
- Copyright
- Files installed from the Distribution Diskette
- Windows DLL and Examples
- DOS 'C' Library and Examples
- Using the Dynamic Link Library
- Windows and DOS Library Functions
- Initialisation Functions
- Interrupt Control Functions
- Data Buffer Functions
- Timer/Counter Functions
- Differential Counter Functions
- Frequency Generation Functions
- Millisecond Stopwatch Functions
- Frequency Input and Output Functions
- Digitally- and Voltage-Controlled Oscillator Functions
- Digital Input/Output Functions
- Switch Scanner Matrix Functions
- Bi-Directional Data Bus Functions
- PC215E Library Error Codes
- PC215E Interface Guide For LABTECH NOTEBOOK
- Guide to User Programming
- Signal Centre
- CONTENTS
- DECLARATION OF CONFORMITY
PC215E Page 42
Bits 5…0 Counter's programmed Mode exactly as written in the last Mode Control Word
Bit 6 State of the addressed counter element
0 Count available for reading
1 Null Count
Bit 7 State of the addressed counter OUT pin
0 OUT pin is '0'
1 OUT pin is '1'
5.3.14 Z2 Counter 0 Data Register
The 82C54 Programmable Timer Counter Z2 provides three 16 bit counter/timers which can be
independently programmed to operate in any one of six modes with BCD or Binary count
functions. The register definition for Z2 Counter 0 Data is as follows.
Register
Offset
Write and/or
Read
Register
Width
Register
Title
Mnemonic
14
16
Write and Read 8 bits
82C54 Counter/Timer Z2
Counter 0 Data Register
Z2 CT0
FUNCTION
The Z2 Counter 0 Data Register is used to write and read 8 bit data to the 82C54 Z2
counter/timer 0. The counter is normally configured for 16 bit operation and to ensure validity of
the data it is important to always write/read two bytes to the register, least significant byte first.
Please note that the 16-bit count values written to this register are not latched into the counting
element until the next clock pulse (assuming the gate input is high). Subsequent read
operations from this register will therefore not reflect the new count value until this clock pulse
has latched the data.
The counter can be configured to operate in several modes. Further details may be found by
reference to the device manufacturer's 82C54 data sheets in the appendices.
The input to counter 0 can be any of the five internal master clock frequencies (10 MHz, 1 MHz,
100 kHz, 10 kHz or 1 kHz), an external clock, the Z2 External Clock signal or the output of Z1
counter 2. This clock source selection is made by writing to the Group Z Clock Connection
Register described in Section 5.3.19.
The output of counter 0 is available on the user socket, SK1 pin 57, and also as a possible clock
source for Z2 counter 1. The inverted output of Z2 counter 0 is also available on SK1 pin 38.
The gate input to counter 0 can be selected as VCC (permanently enabled), GND (permanently
disabled), the inverted output of Z1 Counter 1, or an external gate signal on SK1 pin 18. This
gate selection is made by writing to the Group Z Gate Connection Register described in Section
5.3.20.