Instruction manual

Table Of Contents
Page
39
PC215E
Further information on programming the 82C54 Programmable Counter/Timer is given in
chapters 4 and 6.
BIT ASSIGNMENTS
The bit layout of the Z1 counter 2 data register is shown below.
5.3.12 Counter/Timer Z1 Control Register
The Z1 control register provides the means to configure the three sixteen bit counter/timers of
the 82C54 Z1. An outline of its operation is given here, but reference should be made to the
82C54 device manufacturers’ data sheets in the appendices before programming of the counter
is attempted.
The Counter Timer Control register is a WRITE register. The READ register at the same
location BA + 13
16
returns the status of the 82C54 Z1 Counter/Timer when used with the Read-
Back command.
Register
Offset
Write and/or
Read
Register
Width
Register
Title
Mnemonic
13
16
Write 8 bits
82C54 Z1 Counter/Timer
Control Register
Z1 CTC
FUNCTION
Provides a control word to define the operation of the Z1 counters 0, 1 and 2.
The programming procedure for the 82C54 is flexible, but the following two conventions must be
followed:
For each counter, the control word must be written before the initial count is loaded.
The initial count must follow the count format specified in the control word. This format is
normally least significant byte followed by most significant byte (control word bits 5, 4 = 1 1)
but can be L.S. byte only or M.S. byte only.
01234567
Second Byte
(Most Significant)
8
9
10
11
12
13
14
15
First Byte
(Least Significant)
0
1
2
3
4
5
6
7
Z1 16 BIT COUNTER 2 DATA BIT