Instruction manual

Table Of Contents
Page
5
PC215E
Figure 2 - PC215E Block Diagram
Port C
Port B
Port A
82C55
PPI - Y
Port
C
Port B
Port A
82C55
PPI - X
CTR 2
CTR 1
CTR 0
Address Offset
Decoder
Interrupts Enable and
Status Registers
W/R
5 bit Address
Offset
Event
Interrupt
8 bit
Data
I/O
Bus
82C54
Ctr/Tmr
Z2
82C54
Ctr/Tmr
Z1
CTR 2
C
TR 1
CTR 0
AddressControls DataIRQ
ISA Bus
PC INTERFACE
A0
A1
A2
A3
A4
A5
A6
A7
C0
C1
C2
C3
C4
C5
C6
C7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
C0
C1
C2
C3
C4
C5
C6
C7
B0
B1
B2
B3
OUT0
GAT0
Z1 I/P
Z2 I/P
CLK0
B4
B5
B6
B7
OUT1
GAT1
CLK1
/OUT0
OUT2
GAT2
CLK2
OUT0
GAT0
CLK0
OUT1
GAT1
CLK1
/OUT0
OUT2
GAT2
CLK2
Counter
Connection
Registers
Z1 and Z2
Board Crystal Clock Generator
(5 source frequencies)