Specifications

Page 22
FIREFINDER SERIES II INSTALLATION, COMMISSIONING &
OPERATION
4.17 Addressable Loop Termination Board (BRD86DLTB-B)
The Addressable Loop Termination Board acts as the interface between the external addressable
devices and the control and monitoring functions of the FireFinder. Each board provides
terminations for two loops. One slave CPU is required per loop.
 Note: Apollo devices L2 is +ve (positive), L1 is -ve (negative)
Connect the XP-95 / DISCOVERY loop to the panel as shown below.
AMPAC strongly recommend that the LoopManager test set is used to check that the Apollo loop
has been correctly installed and commissioned before connecting it to the FireFinder™.
Loop Parameters
 126 Apollo Devices (i.e. maximum address range)
 500mA Current Max
 S/C protection circuitry activates at approximately 650mA
 Maximum length 1.2km
Note: To achieve full current, the Loop Trip current in Loop Parameters needs to be set to
300mA (ConfigManager)
CONNECTIONS
CN1 / 2
To 302-699
CN3 / 4
27VDC in / out
TB1 / 2
To Addressable loop devices
REGULATED
27VDC In / Out
T0 SLAVE CPU
CN1
LOOP NORMAL
LED OUT
monitoring
each Loop is ON
LED OUT & IN ON
indicates a fault
on the Loop
( S/C, O/C ) and
the Loop is being
monitored in
both directions
LOOP IN FAULT
R+
L1
L2
-R
L1
L2
-R
L1
L2
-R
R+
R+
Wiring Shown
Above is for a
XP95 Circuit
with one Detector
Having LED
Monitoring
L1
L1
L1
L2
L2
L2
IN
OUT
IN
OUT
BRD86DLTB2-
LOOP 2
LOOP 1
+
-
-
+
+
-
IN
OUT
-
+
+
-
DC
+
-
DC
OUT
IN
LOOP 1 CONTROL
LOOP 2 CONTROL
-5V
+5V
+12V
+40V
0V
LOOP 1 RETURN SENSE
LOOP 2 RETURN SENSE
TRI WAVE
POWER
LOOP1
OU T
IN
LOOP1
OU T
LOOP2
IN
LOOP2
C52
C50
R100
R92
R76
R67
R43
R34
R23
R12
R138
R148
R142
R135
R146
R140
R51
R81
R50
R104
R103
R108
R106
R5
R56
R55
R54
R52
Q26
Q10
Q17
Q15
Q18
Q13
Q11
Q2
Q8
Q6
Q9
Q4
Q1
D12
D13
D6
D5
C17
C41
C97
N1236
R84
R105
R4
R127
R125
R155
R137
R123
R159
R149
R151
R160
R166
R165
R164
Q19
Q23
Q21
D19
D15
C65
C49
C76
C54
C61
C87
C77
C82
C75
C90
C89
C100
C94
U1
U8
U21
U22
R184
R179
R178
R175
R173
R174
R177
R176
C96
C109
C108
C102
C106
C101
C95
U23
ZD23
ZD17
ZD21
ZD22
ZD20
ZD13
ZD16
ZD18
ZD15
ZD14
ZD12
ZD6
ZD10
ZD11
ZD9
ZD2
ZD4
ZD7
ZD5
U9
U7
U12
U10
U5
U14
U16
U20
U3
U2
U19
U6
U4
U13
U15
U18
U17
U24
U25
TH2
TH1
TH3
TB2
TB1
RN1
R139
R62
R63
R71
R85
R57
R83
R119
R61
R86
R113
R87
R93
R89
R114
R122
R77
R121
R120
R134
R66
R64
R97
R143
R158
R168
R110
R167
R147
R136
R2 R3
R9
R37
R30
R111
R38
R115
R39
R40
R118
R112
R20
R116
R117
R131
R133
R44
R141
R157
R163
R109
R162
R145
R181
R180
R182
R183
Q16
Q28
Q7
Q27
L4
L3
L6
L8
L2
L1
L5
L7
L9
D14
D17
D7
D1
D16
D22
D21
CN3 CN4
CN2
CN1
C26
C46
C2
C21
C70
C31
C39
C48
C38
C45
C35
C58
C40
C64
C68
C36
C27
C73
C74
C86
C83
C56
C69
C15
C6
C16
C24
C57
C63
C67
C3
C71
C72
C85
C81
C55
C103
C104
C105
C99
C107
C59
C91
C92
C78
C84
C80
C88
C62
C53
C79
C51
C66
C60
D18
D20
Q22
Q24
Q20
R170 R171
R172
R161
R152
R150
R169
R124
R144
R156
R128
R130
U26
HSNK1
C1
C98
ZD1
R14
R132
RN2
Q25
C34
+
-
+
-
-
-
T0 SLAVE CPU
CN1
Figure 26: Addressable Loop Termination Board