Specifications

BXT7059 / BXTS7059 Technical Reference Chipset Configuration Setup
Chapter 3 Chipset Configuration Setup
Introduction
The term “chipset” is a bit of a misnomer for the Trenton BXT7059 and BXTS7059. The “chipset” on
these SHBs is really a single component called a “Platform Controller Hub” or PCH, and the Trenton
BXT7059 and BXTS7059 both feature the Intel® C604 PCH. The PCH; developed under the code name
Patsburg-B, combines many of the capabilities that were previously contained in individual North Bridge
and South Bridge chipset components. The following section covers the set-up parameters of what could
be thought of as the North Bridge and South Bridge sections of the Intel® C604 Platform Controller Hub.
North Bridge Configuration
The North Bridge Configuration menu item allows the user to do the following:
Option
Description
Sandy Bridge-EN /
Ivy Bridge-EN IOH
Configuration
The Input Output Hub (IOH) configuration menu allows the user to view,
enable or disable the Intel® Virtualization Technology for Directed I/O feature
of the processors. This menu selection is also used to configure the PCI
Express links out of the CPUs. Short operational descriptions for each sub-menu
setting can be found in the upper left corner of the BIOS set-up screen. The
following sub-menu option choices are available for configuration:
Intel® VT for Directed I/O Configuration – Disabled/Enabled (bold = default
setting)
The following configuration choices are available if Intel VT-d is enabled:
Coherency Support: Disabled/Enabled
ATS Support: Disabled/Enabled
Intel® I/O Acceleration Technology (I/OAT): Disabled/Enabled
DCA (Direct Cache Access) Support: Disabled/Enabled
VGA Priority: Offboard
Target VGA: Currently fixed at VGA from CPU0
GEN3 Equalization WA’s (workarounds): Disabled/Enabled – If enabled, the
following four parameters become visible:
Gen3 Equalization Fail WA: Disabled/Enabled
Gen3 Equalization Phase 2/3 WA: Disabled/Enabled
Equalization Phase 2/3 Supported: Disabled/Enabled
Gen3 Equalization Redoing WA: Disabled/Enabled
IOH Resource Selection: Auto/Manual
No Snoop Optimization: VCO/VCP/VC1 / VC1
MMIOH Size: 1G, 2G, 4G, 8G, 16G, 32G, 64G, 126G
MMCFG Base: 0x80000000, 0xA0000000, 0xC0000000
PICMG PCIe Port Bifurcation Control:
PCH Uplink Link Speed: GEN1, GEN2, GEN3
IOB Link Speed: GEN1, GEN2, GEN3
PICMG/PEX10 Port “Ax”: x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16
PICMG PCIe port Data Direct I/O Control:
PCH Uplink Port: Disabled/Enabled
IOB Port: Disabled/Enabled
PICMG/PEX10 Port A0: Disabled/Enabled
PICMG/PEX10 Port A1: Disabled/Enabled
PICMG/PEX10 Port A2: Disabled/Enabled
PICMG/PEX10 Port A3: Disabled/Enabled
3-1 Trenton Systems Inc.