Specifications

Introduction
consists of: an arbitration scheme that allows efficient bus sharing among
multiple EISA masters, the host CPU, Refresh, and DMA devices; a
seven-channel programmable DMA Controller, a 16 level programma-
ble interrupt controller which provides level or edge triggered interrupt
capability on a channel-by-chaneel basis; non-maskable interrupt logic
for multiple NMI control and generatin; five counters/timers which
provide a system timer interrupt, DRAM refresh requests, a fail safe
timer, a speaker tone output, and a periodic CPU speed control. Besides,
SiS85C406 also integrates the imperative glue logic in EISA system to
further minimize the number of board components.
П SiS85C411 (System/Cache/DRAM Controller)
The System/Cache/DRAM Controller provides powerful cache, DRAM
and CPU interfaces utilizing the integration of faster and configurable
memory functions and most efficient cache systems. Its memory logic
circuit can respond to the CPU and EISA burst cycle allowign faster
transfer operations. With its bank (or double-word) memory interleav-
ing, systems at full speed can attain the utmost memory speed.
a SiS85C420 (EISA Bus Controller)
The EISA Bus Controller is a generic EISA Bus Controller which
contains all the necessary logic to control EISA bus cycles in the system
level design. The SiS85C420 provides the state machines that interfaces
to the host, EISA, and ISA buses, and is loosely coupled with SiS85C411
to support 8-, 16-, and 32-bit masters and slaves. SiS85C420, combining
with SiS85C406, creates a full feature of EISA system board.
n SiS85C431 (EISA Data Buffer)
The EISA Data Buffer is a general data path chip that provides all the
data routing and swapping between the host data bus, memory data bus,
and EISA data bus. It also contains parity genertion and detection logic.
• Real-Time Clock
The Real-Time Clock contains a self-contained lithium battery which offers
ten years of data retention capability.
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