Specifications

SL 486VE User's Manual
• DRAM Speed
There will be plenty of timing marging if the user adopts Fastest for 25 MHz,
Faster for 33 MHz, and Slowest for 50 MHz, even when 100ns DRAMs are
used. If 70/ 80ns DRAMs are used, faster speed option can be selected.
• DRAM Write CAS Pulse Width
The option determines the number of wait states to be kept when the CPU
writes data into the local DRAM.
The available options are as follows:
. 2 T
. IT
Ш Cache Write Back
If disabled, cache is write-through. If enabled, cache is write-back. A write-
back cache can offer higher performance than a write-through if writes to
the main memory are much slower than writes to the cache. The write-back
cache is also favored when a memory location is written several times in the
cache before written into the main memory. The performance advantage of
the write-back cache over write-through cache is software dependent.
• Cache Write Cycle
During CPU cycle, it is used as a write latch function to support longer data
hold time for DRAM write, while in hold acknowledge cycle it indicates
cache read hit.
• Cache Burst Read Cycle
Due to constraint for technology, speed of currently available SRAM may
not be high enough to catch up with the speed ofthe CPU, which means that
at every step of program execution, the CPU must wait for the SRAM to
respond. This option determines the number of cycle times to be inserted
when CPU read data to SRAM.
Moreover, the setting depends on the speed of the CPU and SRAM. If the
CPU is of high speed, the timing of SRAM processing data needs an
extension, except for some SRAMs that can be high enough to catch up with
the speed of CPU .
The available options are as follows:
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