Specifications

SL486VE User's Manual
The on-board DRAM beyond the cacheable size is not cacheable for the
secondary cache. It is still cacheable for the 80486 internal cache, however.
To reduce the propagation delay of the chip output buffer, the SiS85C411
employs an "advanced clock" instead of CPU clock to clock the cache read
control signals. The advanced clock should lead CPU clock by 3 to 7 ns. It
will increase the margin of data RAM access time. For 16/20 MHz systems,
the ACLK can be connected to CPUCLK to simplify the clock circuit.
The following is a table of cache configurations and suggested speed ratings
of the SRAM for implementing the cache data RAM for various speeds of the
80486 CPU.
Cache Configuraion
25 MHz CPU
33 MHz CPU 50 MHz CPU
2-1-2 Interleave *
20 ns 20 ns
None
2-1-2 Non-interleave
20 ns None
None
2-2-2 Non-interleave
20 ns 20 ns
None
3-2-3 Non-interleave
20 ns
20 ns 20 ns
3-2-3 Interleave
20 ns
20 ns
20 ns
Note:"*"
x
-y-
z
means x-y-y-y burst read and zT write cycle.
Interleave means two banks Cache (64KB/256KB)
Non-interleave means one bank Cache (128 KB).