Specifications

Memory Configuration
2.1.2 DRAM Module Removal
If possible, use a SIMM extraction tool; otherwise use the following method:
1. Carefully use your thumbs to bend outward the plastic tab ends on both
sides of the slot.
2. The RAM module board will be automatically ejected off the clip arms.
3. Take it out of the socket.
4. Repeat step 1 through 3 to release the other RAM modules.
2.2 Cache Memory Subsystem
For CPU cycles, the content of the cache memory is renewed when either the
cache read miss or write hit occurs. Tag and data RAMs are both updated in
the cache read miss cycles. In the cache write hit cycles, the SiS85C411 updates
only the data RAM. In the cache write miss cycles, the 80486 writes data into
the mam memory (DRAM), while the cache memory remains unchanged. The
alter bits in the write-back cache are reset in the cache update (read miss) cycles
and set in the hit cycles.
When the cache is disabled, all the CPU reads to the cacheable memory are
treated as cache read miss, so both tag and data RAMs are updated. This feature
is used to initialize the cache memory before enabling it.
In DMA/master cycles, the cache data RAM is written when a writen when
hit occurs, to assure the cache coherency. Cache memory is not accessed in
DMA/master write miss or read cycles for write-through cache. For the
write-back cache, DMA/master read hit cycles are conducted to the cache, not
to the DRAM. The following is the Cache size options.
Cache Size
Tag RAM Data RAM Dirty Bit
Cacheable
Size
64 KB 16K x 4 x2
8K x 8 x 8
16K x4x 1 16 MB
128 KB 16K x 4 x2
32K x 8 x 4
16K x4x 1 32 MB
256 KB
16K x 4 x2 32Kx 8 x 8
16K x4x 1 64 MB
Note:The 128 KB Cache memory are installed by 4 pieces of 32K x 8 bit
SRAM on U30, U31, U32, U33.
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