System information

6.2 Host System Inspector
Processor
Cache
DRAM
Audio
CHARM Card
PCI-to-PCI
Bridge
LAN
PCI Local Bus #0
PCI Local Bus #1
Other I/O
Functions
Bridge/
Memory
Controller
Figure 6.1: The PCI bus provides the CHARM card access to the hardware units of the
host computer.
orchestrates the access to the PCI Master Control unit. This enables full PCI access of the
Linux system of the CHARM card. The PCI Master Control registers are:
PCI MASTER ADDRESS contains the PCI address for the next master access.
PCI MASTER COMMAND contains the PCI command for the next master access.
PCI MASTER BYTEENABLE N stores the PCI byteenable signal for the next PCI cycle.
PCI MASTER DATA OUT contains the return value of the PCI Master Control. Normally,
this is the read value of the last PCI read cycle.
PCI MASTER DATA IN contains the data which has to be transferred from the CHARM
to the target device.
PCI MASTER CONTROL is the register to control the state machine of the PCI Master
Control. The start or the stop of a PCI Master access is handled with this register.
PCI MASTER RESET resets the state machine of the PCI Master Control unit.
PCI MASTER STATE contains the state of the PCI Master Control unit.
Figure 6.2 illustrates the communication flow of the PCI Master driver. The signals for
the PCI Master Control are registered using one register for every clock domain. The start
signal activates the PCI Master Control. To save space inside the FPGA, only the start
and the done signal are synchronized to the clock domains using two FIFOs connected in
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