System information

6 Hardware Monitor Functionality

that the system is currently executing [79]. The error or checkpoint code is either a byte

or a word value. The BIOS and mainboard manufactures provide tables assigning the code

value to a certain checkpoint or failure. Most of the POST code tables can be obtained

at the website www.bioscentral.com. As a general rule, the BIOS vendor provides a set of

basic POST codes and the motherboard manufactures extend the POST code set with their

own codes.

The CHARM takes the POST codes from the PCI bus and presents it to the user interface

of the card. Therefore, the CHARM snoops the PCI bus and waits for an I/O access to

port 80h. This is the task of the POST sniﬀer module. Figure 2.3 of chapter 2 shows the

module at the lower part of the picture. It acts passively and does not inﬂuence the PCI

bus. The module runs independently and does not need the PCI core of the CHARM.

It is improved for some computer systems which do not provide the POST code data in

a valid PCI data cycle, instead the POST code was transferred in a PCI retry cycle. In

this system there was no completed PCI data cycle to port 0x80. Hence, write accesses

to the POST code I/O address will never be successful. Additionally, the port address of

the POST sniﬀer is changeable by the Linux system running on the CHARM. This enables

POST code sniﬃng in computer systems using other ports than port 0x80 to transfer POST

codes. The CHARM uses the codes to control the boot process of the host system. For

example, the POST code 0x37 at the test system #1 (see appendix G) means the display

of the CPU information and the entry point of the BIOS setup utility [32]. And the POST

code 0x85 represents the display of an error message and the waiting of a user response.

Chapter 7 describes how the CHARM uses the POST code to perform automatic setup

tasks of a computer system.

6.2 Host System Inspector

The CHARM card analyzes the host computer with the aid of the PCI bus. The name

Host System Inspector combines all functions of the CHARM which inspects actively the

host computer. If a computer system does not start and the system is not operable, the

CHARM card undertakes the system control. Figure 6.1 shows a computer system with an

installed CHARM card. The CHARM card has PCI master capabilities and can access all

hardware units connected to the PCI bus. By the reason of the Linux system running on

the card, the CHARM can initialize and use the hardware devices as well as the operating

system of the host computer [80]. The system can be inspected with regards to which part

of the hardware avoids the booting of the computer. The hardware can be tested step by

step.

The base of the PCI master capability is the PCI Master Control unit which is explained

in the following section, and the related PCI master kernel driver.

6.2.1 PCI Master Control

The PCI Master Control unit interfaces with the master port of the Altera PCI core. It

initiates PCI cycles with the aid of the PCI core. The master control unit is commanded

via the CHARM Register ﬁle. Software running on the ARM CPU can access the CHARM