System information

4.2 Graphic Card Implementation Layout
PCI Core /
PCI Target Control
Request Buffer
Host
CPU
Write #1
success
write to
write to
Processing
success
retry
retry
success
success
write to
write to
write to
success
Time Window
Time Window
Write #2
Write #3
Write #3
Write #4
Write #5
Write #3
Figure 4.10: Timing of the access to the Request Buffer.
released from the software after data processing. To avoid slow down the CHARM system,
there is no second buffer which stores the incoming PCI requests during data processing.
The time while the PCI target control unit stores the PCI requests to the buffer is used
by the CHARM system to convert the VGA data into a VNC framebuffer format (section
4.2.3 explains the VNC server). Figure 4.11 illustrates the synchronization of the access to
the Request Buffer.
The PCI target control unit informs the VGA processing software about the end of the
buffer writing. This is realized by one of the hardware interrupt ports of the ARM CPU.
The software acknowledges the interrupt and starts the read out of the Request Buffer.
The processing software consists of two parts: one for the PCI interface and one for the
VGA processing. The Base Address Register Switch driver (BAR Switch) handles the
Request Buffer and the VGA driver processes the VGA related PCI requests. The data are
read out and processed according to the FIFO (First in First out) principle. Meanwhile,
the PCI target state machine is not permitted to access the Request Buffer. Afterwards,
the BAR switch driver signals to the PCI target control unit about the end of the data
processing. Not till then, the target control unit starts writing to the Request Buffer again.
The acknowledge signal of the driver is realized by a control register. It is part of the
CHARM configuration and control registers, called "CHARM Register". Figure 2.3 shows
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