System information

4 Graphic Card Implementation
Request Buffer
PCI Write #1
PCI Write #2
PCI Write #3
PCI Write #5
Address
PCI Write #6
MARK
PCI Write #4
Request Buffer
PCI Write #8
PCI Write #9
PCI Write #10
PCI Read #1
MARK
Time = X Time = X+1
PCI Write #7
PCI Write #6
PCI Write #7
MARK
Figure 4.9: Two sample Request Buffer contents. The yellow frames mark the valid content
of the buffer.
stops accepting further PCI requests from the host. Therefore, a read request is always the
last valid entry inside the buffer.
Hardware-Software Handshaking
The Request Buffer is also accessible by the processing software running on the ARM CPU.
To avoid raise conditions between the PCI target control unit and the processing software,
mutual access to the Request Buffer is not permitted. The target control unit is allowed to
write to the Request Buffer via a fixed period. PCI requests to the CHARM can be handled
during this time. After the expiration of this term, the processing software gets access to
the buffer. In the meantime, PCI access to the CHARM cannot be processed. The target
control unit terminates the PCI access with a "retry". According to the PCI specification,
the host has to repeat the same request [59]. After data processing the target control unit
gets access to the buffer again. Now, the repeated transaction can be processed. Figure
4.10 depicts this process. The host CPU writes data to the CHARM. The target control
unit takes the requests and saves them to the Request Buffer.
PCI Write #1 and PCI Write #2 are immediately stored. The related data are saved in
the buffer. But PCI Write #3 has to be repeated, because the software is processing the data
and the target control unit loses the access grant to the buffer. The target control unit is
waiting for the end of the data processing. The synchronization of the writing hardware and
the data processing software is time-consuming. For this reason, a single stored data packet
is not immediately processed by the software. Instead, the PCI requests to the CHARM
will be collected in the Request Buffer. However, the video screen has to be displayed in real
time. On this account, the Request Buffer is processed periodically within a fixed period.
Consequential, the buffer size is limited by the number of possible PCI requests within the
specified time interval. The software has no time limit for the buffer access. The buffer is
52