System information

4 Graphic Card Implementation
4.2.2 Hardware Implementation of the PCI Target Interface
The VGA related interface between the host computer and the CHARM is the PCI bus. All
VGA requests of the host are sent over the PCI bus. Thereby, a VGA request is a screen
update or a video mode setting for example. The CHARM contains a PCI core which
interfaces with the PCI bus. It undertakes the low level PCI protocol. More information
about the PCI core can be found in chapter 2 or here [39]. The local side interface of the
PCI core is connected to the PCI target control unit. It processes the access to a PCI base
address of the CHARM. Figure 4.7 illustrates the data flow of the PCI write sent by the
host computer. The picture is a chart of the figure 2.3 of the PLD layout in chapter 2.
PCI
Bus
Data Flow of the
PCI Request
PLD
PLD
Stripe
Bridge
External
SDRAM
Stripe
SDRAM
Controller
AHB
AHB
Master
PCI
Target
Control
PCI
Core
Figure 4.7: Layout of the PCI processing units.
The PCI target control unit does neither process nor interpret the content of the PCI
access. Instead, the target control unit stores all information about the PCI request in
a dedicated buffer. After this, the host will receive the signal that the PCI transfer is
completed. But the data is not processed at this time. More precisely, the written VGA
data is currently not displayed in any way. Normally, the host writes VGA data to the
graphic card. Therefore, the CHARM does not have to return data and can process the
received data at a later time. But there are also VGA read request requiring data from the
CHARM. In this case, the CHARM has to return data as soon as possible to avoid slowing
down the system.
Request Buffer
The buffer storing the PCI requests is called "Request Buffer". It is located in the SDRAM,
the main memory of the CHARM. The buffer is organized like a list. Newly received PCI
requests append to the end of the list. Figure 4.8 depicts the structure of the Request
Buffer.
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