System information

4.2 Graphic Card Implementation Layout
PCI Core
PCI BAR
Hide
PCI Bus
PCI Signals
Host does not see BAR2
PCI Core View PCI BAR Hide View
Host Computer View
Figure 4.6: PCI Configuration Space hiding.
CHARM. The module returns zero to the PCI AD (address/data) bus while the PCI data
phase. The reason is that unimplemented Base Address Registers have to be hardwired to
zero [40]. The signal of the PCI BAR Hide overwrites the signal of the PCI core returning
the hardwired VGA address.
VGA Vertical Retrace Register VGA is an analog display standard. Therefore, some
VGA registers control the output to a CRT Monitor (the CRTC register for example). The
electron beam of a CRT monitor has a vertical retrace. A vertical retrace is the returning
of the electron beam from the lower-right corner of the screen to the upper-left corner.
Operating systems use this time to write new graphic data to the video card. The VGA
input status register (I/O port 0x3DA) provides information about the vertical retrace of
the electron beam. Some operating systems do not work if the content of this register do
not periodically change. Furthermore, this applies also to graphic cards which have only
a digital output. The CHARM has to toggle the content of the status register to avoid
malfunction of the operating system of the host.
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