System information

4 Graphic Card Implementation
BARs. This means that the base address register contains a fixed value or rather an address
window. This window is not changeable at runtime and cannot not be initialized by the
computer BIOS. Two PCI BARs of the Altera PCI core are setup with the VGA address
window 0xA0000-0xBFFFF and the I/O port range from 0x3C0-0x3DF. But these BARs
have to be hidden from the computer system. First, a VGA address window inside the
BAR conflicts to the reserved memory area of the first one megabyte of a computer system.
Second, a "hardwired" BAR does not meet the PCI Specification (except hardwired BARs
to zero) [40]. Therefore, a VHDL module was developed to hide these BARs against PCI
Configuration cycles.
Device ID Vendor ID
Status Command
Class Code
Revision ID
Cache Line
Size
Latency
Timer
Header
Type
BIST
Base Address Registers
(BARs)
Cardbus CIS Pointer
Subsystem ID Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Capabilities
Pointer
Interrupt
Line
Interrupt
Pin
Min_GntMax_Lat
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
3Ch
Reserved
38h
01531 16
10h
14h
18h
1Ch
20h
24h
Memory Region (1MB)
IO Region (64KB)
0xA0000 (128KB)
0x3C0 (32KB)
unused
unused
BAR 0
BAR 1
BAR 2
BAR 3
BAR 4
BAR 5
Figure 4.5: PCI Configuration Space of the CHARM.
Figure 4.5 depicts the content of the Base Address Register inside the PCI Configuration
Space of the PCI core. The first two BARs define a memory region and an I/O port region.
These regions are setup by the computer BIOS while startup. BAR2 and BAR3 contains
the hidden VGA address windows. But these BARs just contain the start address of the
address windows. The size of these hardwired windows is managed inside the PCI core.
Figure 4.6 illustrates the mechanism of the PCI BAR hiding. The PCI BAR Hide module
just answers to PCI Configuration Reads to address 0x18 and 0x1C. These are the locations
of BAR2 and BAR3 inside the PCI Configuration Space. By means of the IDSEL PCI signal,
the BAR Hide module can determine whether the PCI Configuration access belongs to the
48