System information

2.3 FPGA Design of the CHARM
BAR No.. Type Size Function
0 Memory 1 MB Enhanced video function
1 I/O 64 KB BIOS RPC functions
2 Memory 128 KB VGA Memory Region
3 I/O 32 KB VGA I/O Region
Table 2.2: CHARM PCI Base Address Register.
cation port between the CHARM and the VGA BIOS running on the host computer. The
VGA BIOS is explained in section 4.3. The last two BARs implement the VGA address
windows. The VGA protocol and the related address window are explained in section 4.1.
PCI Target Control The PCI target control unit handles accesses to the BAR address of
the PCI core. The received data are commands for the CHARM and have to be processed.
The used FPGA does not provide enough space to process the data inside the FPGA.
Instead, software running on the ARM undertake this task. The target control unit buffers
the address, data and command of the PCI request to the SDRAM memory. Software reads
out the SDRAM and processes the data. Chapter 4 discusses this mechanism precisely.
The target control unit interfaces to the AHB Master module. The PCI target control does
not integrate an own bus master because the used bus system could be exchanged. The
bus master logic was separated from the PCI target logic. Previous FPGA designs use an
Avalon bus master to store the PCI data into the external SRAM. The released SDRAM
memory space could be used to increase the Linux main memory. However, if the CHARM
is not equipped with an external SRAM the card can be produced more cost efficiently.
PCI Master Control The PCI Master Control is connected to the master port of the
Altera PCI Core. It setups the PCI Core to initiated PCI bus cycles. The PCI Master
Control is explained in section 6.2.1 more precisely.
SPI The Serial Peripheral Interface (SPI) is a synchronous serial data link standard de-
veloped by Motorola. The SPI module interfaces to the Analog Digital Converter of the
CHARM. Additionally, the SPI module is addressable by the Avalon bus. The software
running on the ARM can command the ADC unit by the aid of the SPI module. The used
SPI module is an Altera SOPC
8
Builder library component [41].
FAN Speed The FAN Speed module counts the impulses of the computer fans. They are
connected to the CHARM board and provide a digital signal which toggles proportional
with the fan frequency.
Avalon Bus System The Avalon Bus is a simple bus architecture. It is designed for
connecting on-chip processors and peripherals together to a system on a programmable chip
8
System On a Programmable Chip.
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