System information

2.3 FPGA Design of the CHARM
2.2.3 FPGA Device
The embedded stripe of the Excalibur depicted in section 2.2 interfaces with a programmable
logic architecture similar to that of an APEX 20KE [35] device. Altera’s APEX20KE devices
are designed with MultiCore architecture, which combines LUT
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-based and product-term-
based logic. Additionally, the device contains an enhanced memory structure to provide
a variety of memory functions, including CAM, RAM or dual-port RAM. The Excalibur
device EPXA1 contains the APEX20K-100E and is installed on the card. Table 2.1 lists
the features of this device.
Feature Value
Maximum system gates 263.000
Typical gates 100.000
LEs 4.160
Maximum RAM bits 53.248
Table 2.1: Features of the FPGA used in the EPXA1 chip where LE means Logic Element.
2.3 FPGA Design of the CHARM
The communication and control of the hardware components of the CHARM is accomplished
by the FPGA logic. The figure 2.3 shows the layout of the FPGA design of the CHARM.
The FPGA design modules are connected to several bus systems. These bus systems are
accessible by the ARM processor through the Stripe-PLD-Bridge. Therefore the processor
can command the entities and control the hardware interfaces of the card, like PCI and
USB. Command and control utilities are centralized in a logic entity named the CHARM
Register. The content of the registers rules the control units of the hardware interfaces and
is partly directly connected to hardware components on the board. The CHARM Register
is explained subsequently to this section. The other logic modules will be discussed briefly.
The chapters which are related to this modules will illustrate its function more precisely.
Two bus systems are used to connect the entities, the AHB and the Avalon bus. The AHB
bus is a high performance bus from the ARM Ltd. and it is described in [37]. The Avalon
bus is a simple bus architecture designed for connecting on-chip peripherals together. The
Avalon bus is explained in [38].
CHARM Register The CHARM Register is the interface between the software running
on the ARM and the FPGA entities. It is accessible by the AHB bus system. Every register
inside the CHARM Register file relates to an FPGA unit. A C code include file contains
these address map. Appendix D shows the address mapping file. The kernel driver and
software application obtain the address to the related hardware units from this include file.
The PCI master, PCI target, POST code sniffer and the FAN speed module have more than
one configuration register inside the CHARM register file.
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Look Up Table.
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