System information

2 CHARM Architecture
Interrupt
Controller
Watchdog
Timer
Single-Port
SRAM
ARM
Processor
Single-Port
SRAM
Dual-Port
SRAM
Dual-Port
SRAM
Memory
Controller
EBI
AHB1-2
Bridge
UART
SDRAM
Flash
Ethernet
Timer
Stripe-to-PLD
Bridge
Configuration
Logic
PLD-to-Stripe
Bridge
AHB1
Embedded Stripe
PLD Array
AHB2
Figure 2.2: Structure of the Excalibur Embedded Processor Stripe [1].
The internal SDRAM controller is connected to the AHB bus system. The Ethernet chip
and the two 8 MB flash devices are accessible by the EBI
4
bus. The EBI bus is independent
of the AHB bus and is synchronized internally with the AHB bus. The FPGA logic is
addressable via the AHB-PLD bridge. The internal SRAM entities of the Excalibur device
are not used by the CHARM. The FPGA logic is also synchronized with the AHB bus.
This is done by the PLD-Stripe-Bridge.
2.2.2 ARM922T CPU
The ARM CPU [34] is the second submodule of the Excalibur chip [1]. The core is a member
of the ARM9 family of processor cores designed by ARM Ltd.. The processor is a 32-bit
RISC
5
CPU which includes an instruction and a data cache and a memory management
unit (MMU). The Harvard architecture is implemented using a five stage pipeline. An
AMBA bus interface provides the connection to the main memory and the peripherals of
the system.
4
Expansion Bus Interface.
5
Reduce Instruction Set Computing represents a CPU design strategy.
30