System information

2 CHARM Architecture
This chapter explains the hardware units and their organization on the CHARM. Section 2.1
gives an overview of the board architecture. Afterwards, the hardware units are explained
through section 2.2 to section 2.3.
2.1 Overview of the CHARM Board
The different hardware components that form the CHARM system are mounted in a multi
chip module board which PCB
1
consists of 8 layers. As control policy, controlling the
devices, an embedded system is running on the hard-core CPU [34] implemented on the
board. Thereby, an FPGA device [35] contains the control logic for the interfaces between
the processotar and the hardware of the board. The CPU and the FPGA a part of the
Excalibur chip from Altera [1] which is used on the CHARM. Figure 2.1 shows the layout of
the CHARM board and the different hardware units which are explained next in the text.
{
USB mini
connector
Ethernet
connector
External power
supply connector
RS232 serial
connector
Flash
memory
Reset
button
JTAG
connector
Internal USB
connector
Voltage
regulator
Ethernet
chip
32bit PCI
dual voltage
connector
EPXA1
Chip
SDRAM SRAM
Floppy
Connector
Sensor
connector
ADC
}
General
IO pin
EZ-Host
USB controller
(on the backside)
Connector to
the Optocoupler
WOL Connector
Figure 2.1: Layout of the CHARM board.
1
Printed Circuit Board.
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