System information

List of Tables
2.1 Features of the FPGA used in the EPXA1 chip where LE means Logic Element. 31
2.2 CHARM PCI Base Address Register. . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Device driver of the CHARM. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 MTD partitions of the CHARM’s flash memory. . . . . . . . . . . . . . . . . 37
3.3 Directory structure of the Root File System . . . . . . . . . . . . . . . . . . 38
3.4 Default settings of the NFS connection. . . . . . . . . . . . . . . . . . . . . 39
3.5 Directories of the NFS share /mnt/charmserver. . . . . . . . . . . . . . . . . 40
3.6 Content of the card specific subdirectory. . . . . . . . . . . . . . . . . . . . . 40
4.1 VGA address window to access the framebuffer. . . . . . . . . . . . . . . . . 45
4.2 VGA I/O ports controlling the video mode. . . . . . . . . . . . . . . . . . . 46
4.3 Device file system entry of the VGA driver. . . . . . . . . . . . . . . . . . . 57
4.4 Process file system entry of the VGA driver. . . . . . . . . . . . . . . . . . . 58
4.5 RPC Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 Partitions of the SRAM of the USB controller. . . . . . . . . . . . . . . . . 68
5.2 Processing entities of the MSBO device. . . . . . . . . . . . . . . . . . . . . 71
5.3 I/O Ports of the ARM-EZ-Host message protocol. . . . . . . . . . . . . . . 72
5.4 Register of the 8042 keyboard controller. . . . . . . . . . . . . . . . . . . . . 76
6.1 Usage of the ADC ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1 Principal tasks of the CHARM card while testing the HLT nodes. . . . . . . 97
7.2 System failures which are handled by the CHARM card. . . . . . . . . . . . 101
8.1 Features of the CHARM PCI bus analyzer. . . . . . . . . . . . . . . . . . . 104
9.1 Typical periodical VGA access sequence of the AMI BIOS running a graphic
mode. The first I/O write (to 0x3CE) is done once only. It sets up the
target register for the I/O writes to port 0x3CF. The next three accesses are
repeated periodically, whereas the memory addresses and values are changed.
The idle time is the period between two VGA accesses. . . . . . . . . . . . 114
9.2 VGA access sequence of a booting Linux kernel running a VGA text mode.
The idle time is the period between two VGA accesses. . . . . . . . . . . . . 115
9.3 VGA performance overview for the VGA requests shown in table 9.1 and
table 9.2. The access period is calculated on the time between two VGA
requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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