System information

List of Figures
1.1 Overview of the LHC ring at CERN. . . . . . . . . . . . . . . . . . . . . . . 19
1.2 The HLT cluster nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Remote management of computer systems. . . . . . . . . . . . . . . . . . . . 22
1.4 Screenshot of a VNC session while setup the BIOS settings with the aid of
the CHARM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5 Screenshot of the web page provided by the CHARM. . . . . . . . . . . . . 25
2.1 Layout of the CHARM board. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Structure of the Excalibur Embedded Processor Stripe [1]. . . . . . . . . . . . . 30
2.3 Structure of the CHARM PLD design. . . . . . . . . . . . . . . . . . . . . . . . 32
3.1 Boot process of the CHARM. First, the boot loader is executed from flash.
Afterwards, the boot code is copied to the SDRAM and is started from the
RAM. The console output of the CHARM is shown on the right side of the
picture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 CHARMs connects to the NFS-Server after boot up. . . . . . . . . . . . . . 39
4.1 Diagram of the VGA data processing. The arrows describes the data flow. . 42
4.2 Layout of the attribute byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 Organization of the video planes in alphanumeric mode. . . . . . . . . . . . . . . 44
4.4 The screen is divided into odd and even columns. . . . . . . . . . . . . . . . 45
4.5 PCI Configuration Space of the CHARM. . . . . . . . . . . . . . . . . . . . . . 48
4.6 PCI Configuration Space hiding. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.7 Layout of the PCI processing units. . . . . . . . . . . . . . . . . . . . . . . . . 50
4.8 Structure of the Request Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.9 Two sample Request Buffer contents. The yellow frames mark the valid
content of the buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.10 Timing of the access to the Request Buffer. . . . . . . . . . . . . . . . . . . 53
4.11 Timing of the access to the Request Buffer. . . . . . . . . . . . . . . . . . . 54
4.12 Request Buffer access synchronization. . . . . . . . . . . . . . . . . . . . . . 55
4.13 Processing of the Request Buffer. The BAR Switch driver reads out the
content and distribute the data to the processing drivers. . . . . . . . . . . . 56
4.14 Processing of read requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.15 Data format of a RPC message. . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.16 Sending of an RPC message. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.17 Receiving of an RPC message. . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.18 Data flow of a host initiated RPC command. The dark boxes mark hardware
components and the white ones software units. . . . . . . . . . . . . . . . . 64
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