System information

8 Special Implementations
The main function of the CHARM is the remote management of the HLT cluster nodes.
However, the CHARM is used in other fields. Thereby, special firmware implementations
enable new functions of the card. The base system of the card (boot-loader, the Linux
kernel and the base root file system) is not changed in this process. The difference are the
FPGA logic and the related Linux device driver. Two further functions are used with the
CHARM card: a PCI Bus Analyzer and a network card. The CHARM has the advantage
that the function of the card can be changed at runtime due to the reconfigurable logic
inside.
FPGA Reconfiguration The FPGA unit of the Excalibur chip is programmable with the
aid of the embedded ARM CPU [97][46]. The ARM CPU can reconfigure the FPGA at
runtime. For this reason, the CHARM card can change its function without rebooting the
board. The PLD device driver provides access to the FPGA unit. The programming file
for the FPGA is generated by the Altera Quartus synthesis software. Quartus is a software
to synthesis and route FPGA logic for Altera PLD devices. The following shell command
illustrates the reconfiguration of the FPGA.
charm:/> dd if=new_fpga_design.sbi of=/dev/pld
The dd utility copies data from one file to another. The PLD device is implemented as a
character device. The used FPGA cannot be programmed in parts. Before the FPGA will
be programmed, the device drivers using the PLD interface has to be unloaded. Missing
hardware units of a device driver may crash the whole system. Furthermore, the devices
have to be reinitialized by the device driver.
8.1 PCI Bus Analyzer
One of the special implementation of the CHARM, is the usage on a PCI bus analyzer. A
PCI bus analyzer is a device which monitors the bus traffic and decodes and displays the
data. It can be used during development of hardware or device drivers, diagnosing bus or
device failures. In contrast to the FPGA logic of the remote management implementation,
the FPGA design of the CHARM PCI bus analyzer does not contain any PCI core. Instead,
all PCI bus signals connected to the FPGA are used as input signals. The signals are
inspected via a final state machine (FSM) to detect a valid PCI data cycle [2].
Table 8.1 shows the features of the CHARM as a PCI bus analyzer. They are not limited
by the reason of logic space, hardware constraints or difficulties of development. It rather
displays the state of work.
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