User`s guide

T-MOPSlcdSA User's Guide
Watchdog Timer 34
34
17. Watchdog Timer
The watchdog timer is integrated in the ATLAS CPU of the T-MOPSlcdSA and can generate a NMI or a
reset to the system. The watchdog timer circuit has to be triggered within a specified time by
application software. If the watchdog timer is not triggered because proper software execution
fails or a hardware malfunction occurs, it generates a NMI or resets the system.
17.1 Configuration
You can set the watchdog timer to enabled or disabled. You can specify the delay time and timeout
(trigger period) from 15 seconds up to 30:15 minutes. The delay time is the time after first
initialization before the trigger period starts. The timeout is the time the watchdog has to be
triggered within. If the watchdog timer is not triggered within the timeout period, the board will
be reset or a NMI is generated. You can make the initialization settings in the BIOS setup utility.
Refer to the “Watchdog Submenu” section in the “Appendix B: BIOS Operation” chapter for
information on configuration.
17.2 Programming
17.2.1 Initialization
You can initialize the watchdog timer from the BIOS setup and out of the application software with
help of the JUMPtec Intelligent Device Architecture (JIDA) programmer’s interface. For BIOS setup
options refer to the “Watchdog Submenu” section of the “Appendix B: BIOS Operation” chapter.
17.2.2 Trigger
The watchdog timer needs to be triggered out of the application software within the specified
timeout period. You can only do this in the application software with help of the JIDA
programmer’s interface.
For information about the JIDA programmer’s interface, refer to the JIDA BIOS extension section
in the Appendix B: BIOS chapter and separate documents available in the JIDA software packages
on the Kontron Web site.