User`s guide

T-MOPSlcdSA User's Guide
Ethernet Interface 30
30
15. Ethernet Interface
The Ethernet interface of the T-MOPSlcdSA is realized with the 82551IT from Intel®, a fully
integrated 10BASE-T/100BASE-TX LAN solution. The 82551IT consists of both the Media Access
Controller (MAC) and the physical layer (PHY) interface combined into a single component
solution. The 32-bit PCI controller provides enhanced scatter-gather bus mastering capabilities
and enables the 82551IT to perform high-speed data transfers over the PCI bus. Two large transmit
and receive FIFOs of 3 Kbytes each help prevent data underruns and overruns while waiting for bus
accesses.
The 82551IT can operate in either full duplex or half duplex mode. In full duplex mode, the
82551IT adheres with the IEEE 802.3x Flow Control specification. Half-duplex performance is
enhanced by a proprietary, collision-reduction mechanism. The 82551IT also includes an interface
to a serial (4-pin) EEPROM. The EEPROM provides power-on initialization for hardware and software
configuration parameters.
The 82551IT provides the following features:
 Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY
 Glueless 32-bit PCI master interface
 Improved dynamic transmit chaining with multiple priorities transmit queues
 Full Duplex support at both 10 and 100Mbps
 IEEE 802.3u Auto-Negotiation support
 3 KB transmit and 3 KB receive FIFOs
 Fast back-to-back transmission support with minimum interframe spacing
 IEEE 802.3x 100BASE-TX Flow Control support
 Adaptive Technology
 TCP/UDP checksum offload capabilities
 Low power 3.3 V device
 Clock run protocol support
Notes:
The Ethernet interface works according to the common criteria of the embedded technology market
segment.