User`s guide

T-MOPSlcdSA User's Guide
CPU,Chipset and Super-I/O 12
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5. CPU, Chipset and Super-I/O
5.1 CPU and Chipset
The T-MOPSlcdSA comes with a STMicroelectronics STPC® ATLAS, which operates with a 120MHz
CPU. The processor and chipset provide a general purpose PC-compatible subsystem on a single
chip. It integrates a standard 5th generation x86 core along with a powerful UMA graphics/video
chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with
standard I/O interfaces to provide a single PC compatible subsystem on a single device.
The chipset integrated in the STPC® ATLAS microcontroller features:
 Integrated PCI North / South Bridge controller
 SDRAM controller (64 bit, 60MHz)
 PCI controller (PCI 2.1 compatible)
 Integrated PCI arbitration interface
 PCI-to-ISA translation cycles
 Translation of ISA master initiated cycles to PCI
 ISA / Master / Slave / DMA
 ISA master / slave supports flash ROM
 ISA hidden refresh
 16bit I/O decoding
 EIDE controller (ATA-1 compatible)
 DMA controller (2x8237/AT compatible)
 Interrupt controller (2x8259/AT compatible)
 Timer/counters (8254 compatible)
 Power Management Unit
5.2 CPU and Chipset Configuration
See the “Chipset Menu” section of the “Appendix B: BIOS Operation” chapter for information on
possible settings.