Specifications

Product Errata 99
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
373 Processor Write to APIC Task Priority Register May Cause
Error Status Bit to Set
Description
The processor may set Error Status Register[Send Accept Error] (APIC280[2]) after a write to a Task
Priority Register (APIC080). This can occur only if a write to APIC080 follows a write to an Interrupt
Command Register (APIC3[1, 0]0) that triggers an interprocessor interrupt (IPI).
This erratum does not apply if the IPI message type set on APIC3[1, 0]0[10:8] is 011b (remote read),
or if an L3 cache is present.
Potential Effect on System
Software may observe and report a false APIC error.
Suggested Workaround
If an L3 cache is not present as indicated by CPUID Fn8000_0006_EDX[L3Size] (CPUID
Fn8000_0006_EDX[31:18]) being equal to zero, system software should set MSRC001_001F[57] to
1b.
Fix Planned
No