Specifications

96 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
362 Illegal Packet on HyperTransport™ Link May Prevent Warm
Reset
Description
The processor may fail to drive external pins to their reset pattern when warm reset is asserted, and
may fail to restart after warm reset is subsequently deasserted, when both of the following conditions
are satisfied:
• The processor has received an illegal packet from a non-coherent HyperTransport™ link with a
specific encoding only used on coherent links. This packet may be detected near a warm reset as
the processor may sample packets on the link for a brief time after warm reset is asserted. On
some platforms, the conditions under which the processor may receive an illegal packet near a
warm reset may not be observed. If link retry mode is enabled, this erratum applies only if the
incoming illegal packet contains a valid CRC.
• One or more processor cores is in the C1 halt state with clocks ramped down. If C1 ACPI Power
State Control Registers [CpuPrbEn] (F3x84[24]) = 1b, clocks are considered as ramped down for
a processor core in the C1 halt state for any valid setting of F3x84[31:29] (ClkDivisor) other than
000b.
Potential Effect on System
System hang during a warm reset. This erratum does not impact cold reset or INIT.
Suggested Workaround
None required for platforms that do not observe this issue. For other platforms, platform BIOS should
set a global SMI trap on any write to a port that could cause warm reset to assert, and then execute the
write from within the SMI handler. This ensures that no cores have clocks ramped down when warm
reset is asserted. This workaround is not effective for warm resets that are initiated without a software
write to a port that can be trapped.
Fix Planned
Yes