Specifications

74 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
322 Address and Command Fine Delay Values May Be Incorrect
Description
The DRAM phy uses the memory speed at the time of DRAM initialization or self-refresh exit to
adjust the fine delay values based on internal DLL settings. Data written to fine delay registers prior
to DRAM initialization or self-refresh exit may be adjusted incorrectly.
No effect is observed for all fine delays except those in the DRAM Address/Command Timing
Control Register at F2x[1,0]9C_x04; these are written after DRAM initialization. However,
F2x[1,0]9C_x04 may be written before DRAM initialization or self-refresh exit and may result in an
incorrect adjustment.
This erratum only affects MEMCLK frequencies of 400 MHz and higher.
Potential Effect on System
The system may have degraded memory margins leading to unreliable DRAM signaling.
Suggested Workaround
The following workaround should be applied by BIOS prior to writing F2x[1,0]9C_x04 during
DRAM controller (DCT) initialization and during the S3 resume sequence:
1. Write 00000000h to F2x[1,0]9C_xD08E000.
2. In unganged mode (DRAM Controller Select Low Register [DctGangEn] (F2x110[4]) = 0b), if
DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is greater than or equal to 011b,
write 00000080h to F2x[1,0]9C_xD02E001, else write 00000090h to F2x[1,0]9C_xD02E001.
3. In ganged mode (DRAM Controller Select Low Register [DctGangEn] (F2x110[4]) = 1b), if
DRAM Configuration Register[MemClkFreq] (F2x94[2:0]) is greater than or equal to 011b, write
00000080h to F2x9C_xD02E001 and F2x19C_xD02E001, else write 00000090h to
F2x9C_xD02E001 and F2x19C_xD02E001.
The write of 00000090h to F2x[1,0]9C_xD02E001 is not necessary if BIOS can not change the
memory clock speed without a cold reset.
Fix Planned
No