Specifications

Product Errata 65
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
298 L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
Description
The processor operation to change the accessed or dirty bits of a page translation table entry in the L2
from 0b to 1b may not be atomic. A small window of time exists where other cached operations may
cause the stale page translation table entry to be installed in the L3 before the modified copy is
returned to the L2.
In addition, if a probe for this cache line occurs during this window of time, the processor may not set
the accessed or dirty bit and may corrupt data for an unrelated cached operation.
Potential Effect on System
One or more of the following events may occur:
• Machine check for an L3 protocol error. The MC4 status register (MSR0000_0410) is
B2000000_000B0C0Fh or BA000000_000B0C0Fh. The MC4 address register
(MSR0000_0412) is 26h.
• Loss of coherency on a cache line containing a page translation table entry.
• Data corruption.
Suggested Workaround
BIOS should set MSRC001_0015[3] (HWCR[TlbCacheDis]) to 1b and MSRC001_1023[1] to 1b.
In a multiprocessor platform, the workaround above should be applied to all processors regardless of
revision when an affected processor is present.
Fix Planned
Yes