Specifications

62 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
293 Memory Instability After PWROK Assertion
Description
The DRAM DQS DLL may not lock properly after PWROK is asserted.
Potential Effect on System
The system may have degraded memory margins leading to unreliable DRAM signaling. In some
circumstances, this may cause BIOS to degrade the memory speed.
Suggested Workaround
During DRAM controller (DCT) initialization, system software should perform the following
workaround to every enabled DCT in the system:
1. Perform a dummy DRAM read to any address on any DIMM attached to the DCT.
2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.
3. Wait at least 300 nanoseconds.
4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C.
5. Wait at least 2 microseconds.
When exiting from the S4 or S5 state, apply the workaround immediately prior to the Receiver Enable
Training. During resume from the S3 state, apply the workaround after F2x[1, 0]90[ExitSelfRef] has
been cleared and prior to restoring the F2x[1, 0]9C registers.
Fix Planned
Yes