Specifications

54 Product Errata

41322 Rev. 3.84 August 2011

Revision Guide for AMD Family 10h Processors

263 Incompatibility With Some DIMMs Due to DQS Duty Cycle

Distortion

Description

Some DIMMs exhibit a duty cycle distortion on the first DQS pulse of an incoming read request

which may cause the processor's DRAM interface to miss a beat of data in a read burst.

Potential Effect on System

Undefined system behavior due to incorrect read data.

Suggested Workaround

If the memory is DDR2-533 or DDR2-667 or DDR3-667 write 00000800h to

F2x[1,0]9C_xD040F30, else write 00000000h to F2x[1,0]9C_xD040F30.

The write of 00000000h to F2x[1, 0]9C_xD040F30 is not necessary if BIOS can not change the

memory clock speed without a cold reset or if BIOS does not support the above mentioned memory

configurations.

When exiting from the S4 or S5 state, apply this workaround prior to setting DRAM Configuration

Low Register[InitDram] (F2x[1,0]90[0]). In addition, for the above mentioned memory

configurations, BIOS should set the DRAM read DQS timing control loop range to 32 during DQS

position training.

When exiting from the S3 state, apply this workaround prior to setting DRAM Configuration Low

Fix Planned