Specifications
Product Errata 33
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
393 Performance Monitor May Count Fastpath Double Operation
Instructions Incorrectly
No fix planned
395 Incorrect Data Masking in Ganged DRAM Mode X
396 VLDT Maximum Current Specification Exceeded at
HyperTransport™ Link Transfer Rates Up to 2.0 GT/s
XXXXXXXXX
397 VLDT Maximum Current Specification Exceeded on
HyperTransport™ Links in Retry Mode
XX
398 HyperTransport™ Links In Retry Mode May Experience High
Bit Error Rate At Specific Link and Northbridge Clock
Frequencies
X
399 Memory Clear Initialization May Not Complete if DCT0 Fails
Training
No fix planned
400APIC Timer Interrupt Does Not Occur in Processor C-States XXXXXXXXXXXX
405HyperTransport™ Link May Fail to Complete Training XXXXXXXXX
406 Processor Does Not Perform BmStsClrOnHltEn Function X
407 System May Hang Due to Stalled Probe Data Transfer XXXX X
408 Processor AltVID Exit May Cause System Hang X X X
411 Processor May Exit Message-Triggered C1E State Without an
Interrupt if Local APIC Timer Reaches Zero
XX
414 Processor May Send Mode Register Set Commands to DDR3
DIMM Incorrectly
XXXXXXXXX
415 HLT Instructions That Are Not Intercepted May Cause System
Hang
No fix planned
416 DRAM Error Injection May Interfere With Power Management
Events
No fix planned
417 Processor May Violate Tstab for Registered DDR3-1333
DIMMs
X
418 Host Mapping of Physical Page Zero May Cause Incorrect
Translation
No fix planned
419 C32r1 Package Processor May Report Incorrect PkgType X
420 Instruction-Based Sampling Engine May Generate Interrupt
that Cannot Be Cleared
No fix planned
421 Performance Monitors for Fence Instructions May Increment
Due to Floating-Point Instructions
No fix planned
437 L3 Cache Performance Events May Not Reliably Track
Processor Core
XXXX X XXX
438 Access to MSRC001_0073 C-State Base Address Results in a
#GP Fault
X
439 DQS Receiver Enable Training May Find Incorrect Delay Value X X X X X
440 SMM Save State Host CR3 Value May Be Incorrect No fix planned
441 Move from Stack Pointer to Debug or Control Register May
Result in Incorrect Value
No fix planned
Table 27. Cross-Reference of Product Revision to Errata (Continued)
No. Errata Description
Revision Number
DR-BA
DR-B2
DR-B3
RB-C2
BL-C2
DA-C2
RB-C3
BL-C3
DA-C3
HY-D0
HY-D1
PH-E0