Specifications

MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) 29
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
Table 26. Cross Reference of Product Revision to OSVW ID
CPUID
Fn0000_0001_EAX
(Mnemonic)
MSRC001_0141 Bits
For single-link processors
(AM2r2, AM3, ASB2, S1g3,
S1g4)
For multiple-link processors (Fr2, Fr5,
Fr6, G34r1, C32r1)
00100F2Ah (DR-BA)
0000_0000_0000_000Fh
1
0000_0000_0000_000Dh
00100F22h (DR-B2)
0000_0000_0000_000Fh
1
0000_0000_0000_000Dh
00100F23h (DR-B3)
0000_0000_0000_000Eh
1
If all processors in the system are revision
DR-B3 processors then
0000_0000_0000_000Ch, else
0000_0000_0000_000Dh when mixed with
DR-BA or DR-B2 processors
00100F42h (RB-C2)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F52h (BL-C2)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F62h (DA-C2)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F43h (RB-C3)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F53h (BL-C3)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F63h (DA-C3)
0000_0000_0000_000Eh
1
0000_0000_0000_000Ch
00100F80h (HY-D0) N/A
0000_0000_0000_000Ch
00100F81h (HY-D1) N/A
0000_0000_0000_000Ch
00100F91h (HY-D1) N/A
0000_0000_0000_000Ch
00100FA0h (PH-E0)
0000_0000_0000_000Eh
1
N/A
1. BIOS may optionally clear OSVW[1] if BIOS does not enable C1E support using
MSRC001_0055[C1eOnCmpHalt or SmiOnCmpHalt].