Specifications

MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) 27
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
MSRC001_0140 OS Visible Work-around MSR0
(OSVW_ID_Length)
This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System
Programming, order# 24593, is used to specify the number of valid status bits within the OS Visible
Work-around status registers.
The reset default value of this register is 0000_0000_0000_0000h.
BIOS shall program the OSVW_ID_Length to 0004h prior to hand-off to the OS.
Bits Description
63:16 Reserved.
15:0 OSVW_ID_Length: OS visible work-around ID length. Read-write