Specifications

146 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
670 Segment Load May Cause System Hang or Fault After State
Change
Description
Under a highly specific and detailed set of conditions, a segment load instruction may cause a failure
in one of the following instructions later in the instruction stream:
• BTC mem, imm8
• BTC mem, reg
• BTR mem, imm8
• BTR mem, reg
• BTS mem, imm8
• BTS mem, reg
• RCL mem, cl
• RCL mem, imm
• RCR mem, cl
• RCR mem, imm
• SHLD mem, reg, imm
• SHLD mem, reg, cl
• SHRD mem, reg, imm
• SHRD mem, reg, cl
• XCHG mem, reg (uses an implicit LOCK prefix)
• XCHG reg, mem (uses an implicit LOCK prefix)
• Any instruction with an explicit LOCK prefix in the instruction opcode.
Potential Effect on System
For affected instructions that have an implicit or explicit LOCK prefix, a system hang occurs.
For affected instructions that do not have an implicit or explicit LOCK prefix, the processor may
present a #PF exception after some of the instruction effects have been applied to the processor state.
No system effect is observed unless the page fault handler has some dependency on this interim
processor state, which is not the case in any known operating system software. This interim state does
not affect the ability for the operating system to handle the #PF and resume the instruction without
impact to the program. However, this interim state may be observed by a debugger or if the operating
system changes the #PF to a program error (for example, a segmentation fault).
Suggested Workaround
†
System software should set MSRC001_1020[8] = 1b.
†
This workaround ensures that instructions with an implicit or explicit LOCK prefix do not cause a
system hang due to this erratum. However, instructions may still present a #PF after altering
architectural state.
Fix Planned
No