Specifications

Product Errata 145
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
669 Local Vector Table Interrupt May Cause C1E Entry Without
Caches Flushed
Description
An interrupt assigned to the APIC local vector table (LVT) that becomes pending in a short interval
around entry to C1E mode may cause the processor to incorrectly enter C1E mode after storing the
interrupt vector but before executing the first instruction of the interrupt handler.
When this occurs, the processor is in C1E mode while the processor caches are not flushed. I/O
activity that occurs while in C1E mode may cause additional and unexpected core clock frequency
changes in order to probe these caches. A short LDTSTOP# assertion time may create a condition
where the processor cores are still performing clock frequency changes when LDTSTOP# is de-
asserted, even when the LDTSTOP# assertion time is greater than the minimum required assertion
time.
The interrupt handler for this LVT interrupt is only processed after the processor exits C1E mode for
another interrupt.
Potential Effect on System
A system hang may be observed if the operating system enters C1 state (by execution of the HLT
instruction) with only a one-shot APIC timer interrupt configured, since the processor is in C1E state
until another interrupt occurs. A system hang has not been observed in silicon. The standard use of
these interrupts, including the APIC timer, does not expose this effect.
LVT interrupts may be delayed while the processor is in C1E low-power state. The standard use of
these interrupts, including the APIC timer, does not make this effect significant.
In addition, if LDTSTOP# is de-asserted while the processor is performing additional and unexpected
core clock frequency changes due to the additional cache probing caused by this erratum, the
conditions described in erratum #610 may be observed. Unless the BIOS or system software has
applied the suggested workaround of erratum #610 (i.e. F3x1B8[5] is 0b), then the processor may
generate an uncorrectable machine check exception (#MC) and a possible sync flood due to a falsely
reported L3 LRU or tag error. Refer to erratum #610 for the MC4_STATUS signature of this machine
check.
Suggested Workaround
Contact your AMD representative for information on a BIOS update.
Implementing this workaround does not alter the minimum LDTSTOP# assertion time.
Fix Planned
No