Specifications

134 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
439 DQS Receiver Enable Training May Find Incorrect Delay Value
Description
Under highly specific and internal conditions, the algorithm for DQS Receiver Enable Training may
incorrectly place the delay value for the DRAM DQS Receiver Enable Timing Control Register
F2x[1,0]9C_x[2B:10] before the read preamble. The conditions under which this erratum may be
observed are sensitive to platform memory configurations and the timing between successive training
data reads.
Potential Effect on System
When the DQS Receiver Enable delay is placed before the read preamble, later DQS Position
Training failures will result in the DIMM being reported in error due to a training failure. The DIMM
may be removed from the configuration.
Suggested Workaround
Contact your AMD representative for information on a BIOS update.
Fix Planned
No