Specifications

Product Errata 131
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
421 Performance Monitors for Fence Instructions May Increment
Due to Floating-Point Instructions
Description
The processor may increment the count for LFENCE, SFENCE or MFENCE instructions
(Performance Event Select Register (PERF_CTL[3:0]) MSRC001_000[3:0][EventSelect] is 1D3h,
1D4h or 1D5h respectively) when unrelated floating-point operations are executed.
Potential Effect on System
Performance monitoring software will not have an accurate count of LFENCE, SFENCE, or
MFENCE instructions.
Suggested Workaround
None.
Fix Planned
No